| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-10-02 | Removed api error port and added error bit in status register that is set ↵ | Joachim Strömbergson | |
| when api access violations happens and cleared by writing the status register. | |||
| 2015-10-02 | Fixing text error in comment. | Joachim Strömbergson | |
| 2015-07-17 | fix CORE_VERSION to match what we think it should be | Paul Selkirk | |
| 2015-05-28 | Corrected where config bits are. | Joachim Strömbergson | |
| 2015-05-16 | (1) Changed name and version to reflect that it is not only AES-128 and that ↵ | Joachim Strömbergson | |
| the core is fairly close to done. (2) Moved counter update. | |||
| 2015-05-04 | (1) Changed ordet of status and config addresses to conform to what we have ↵ | Joachim Strömbergson | |
| in other cores. (2) Changed to localparam to stop polluting namespace. | |||
| 2014-11-28 | Reworked the sbox and inverse sbox. Slighly smaller design and much shorter ↵ | Joachim Strömbergson | |
| source files. | |||
| 2014-11-28 | Removed obsolete target. | Joachim Strömbergson | |
| 2014-11-27 | Adding Makefile for building simulation targets. | Joachim Strömbergson | |
| 2014-11-27 | Adding Python models for AES as well as key expansion and rcon. | Joachim Strömbergson | |
| 2014-11-27 | Adding testbenchs. | Joachim Strömbergson | |
| 2014-11-27 | Adding RTL source files for the AES core. | Joachim Strömbergson | |
| 2014-11-27 | Adding license file too. | Joachim Strömbergson | |
| 2014-11-27 | Adding readme for the aes core. | Joachim Strömbergson | |
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index : core/cipher/aes | |
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) | git repositories |
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