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-rw-r--r--src/rtl/aes_core.v7
-rw-r--r--src/rtl/aes_key_mem.v18
2 files changed, 11 insertions, 14 deletions
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v
index 7c5720d..b74fdc4 100644
--- a/src/rtl/aes_core.v
+++ b/src/rtl/aes_core.v
@@ -154,15 +154,10 @@ module aes_core(
.round(muxed_round_nr),
.round_key(round_key),
- .ready(key_ready),
-
- .sboxw(keymem_sboxw),
- .new_sboxw(new_sboxw)
+ .ready(key_ready)
);
- aes_sbox sbox_inst(.sboxw(keymem_sboxw), .new_sboxw(new_sboxw));
-
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index 496fc08..e3aec4b 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -47,11 +47,7 @@ module aes_key_mem(
input wire [3 : 0] round,
output wire [127 : 0] round_key,
- output wire ready,
-
-
- output wire [31 : 0] sboxw,
- input wire [31 : 0] new_sboxw
+ output wire ready
);
@@ -109,7 +105,8 @@ module aes_key_mem(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [31 : 0] tmp_sboxw;
+ reg [31 : 0] sboxw;
+ wire [31 : 0] new_sboxw;
reg round_key_update;
reg [3 : 0] num_rounds;
@@ -122,7 +119,12 @@ module aes_key_mem(
//----------------------------------------------------------------
assign round_key = tmp_round_key;
assign ready = ready_reg;
- assign sboxw = tmp_sboxw;
+
+
+ //----------------------------------------------------------------
+ // S-box for key expansion.
+ //----------------------------------------------------------------
+ aes_sbox sbox_inst(.sboxw(sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
@@ -223,7 +225,7 @@ module aes_key_mem(
w7 = prev_key1_reg[031 : 000];
rconw = {rcon_reg, 24'h0};
- tmp_sboxw = w7;
+ sboxw = w7;
rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
trw = rotstw ^ rconw;
tw = new_sboxw;