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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-10-02 15:45:11 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-10-02 15:45:11 +0200
commit376d5ad3b631bab9dd9617246815845e7f81ec47 (patch)
treec6962d62d95c790546e0bb4056b5bfaf1bb2e2a7 /src
parent28a9cddf2fa7e934ea790b0e59fcbeddf0c125bc (diff)
Removed unnedded code blocks.
Diffstat (limited to 'src')
-rw-r--r--src/rtl/aes.v195
1 files changed, 49 insertions, 146 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index 7b422b5..033ed89 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -51,6 +51,7 @@ module aes(
output wire [31 : 0] read_data
);
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -244,14 +245,10 @@ module aes(
error_reg <= error_new;
if (init_we)
- begin
- init_reg <= init_new;
- end
+ init_reg <= init_new;
if (next_we)
- begin
- next_reg <= next_new;
- end
+ next_reg <= next_new;
if (config_we)
begin
@@ -260,64 +257,40 @@ module aes(
end
if (key0_we)
- begin
- key0_reg <= write_data;
- end
+ key0_reg <= write_data;
if (key1_we)
- begin
- key1_reg <= write_data;
- end
+ key1_reg <= write_data;
if (key2_we)
- begin
- key2_reg <= write_data;
- end
+ key2_reg <= write_data;
if (key3_we)
- begin
- key3_reg <= write_data;
- end
+ key3_reg <= write_data;
if (key4_we)
- begin
- key4_reg <= write_data;
- end
+ key4_reg <= write_data;
if (key5_we)
- begin
- key5_reg <= write_data;
- end
+ key5_reg <= write_data;
if (key6_we)
- begin
- key6_reg <= write_data;
- end
+ key6_reg <= write_data;
if (key7_we)
- begin
- key7_reg <= write_data;
- end
+ key7_reg <= write_data;
if (block0_we)
- begin
- block0_reg <= write_data;
- end
+ block0_reg <= write_data;
if (block1_we)
- begin
- block1_reg <= write_data;
- end
+ block1_reg <= write_data;
if (block2_we)
- begin
- block2_reg <= write_data;
- end
+ block2_reg <= write_data;
if (block3_we)
- begin
- block3_reg <= write_data;
- end
+ block3_reg <= write_data;
end
end // reg_update
@@ -390,7 +363,6 @@ module aes(
if (we)
begin
case (address)
- // Write operations.
ADDR_CTRL:
begin
init_set = write_data[CTRL_INIT_BIT];
@@ -404,69 +376,43 @@ module aes(
end
ADDR_CONFIG:
- begin
- config_we = 1;
- end
+ config_we = 1;
ADDR_KEY0:
- begin
- key0_we = 1;
- end
+ key0_we = 1;
ADDR_KEY1:
- begin
- key1_we = 1;
- end
+ key1_we = 1;
ADDR_KEY2:
- begin
- key2_we = 1;
- end
+ key2_we = 1;
ADDR_KEY3:
- begin
- key3_we = 1;
- end
+ key3_we = 1;
ADDR_KEY4:
- begin
- key4_we = 1;
- end
+ key4_we = 1;
ADDR_KEY5:
- begin
- key5_we = 1;
- end
+ key5_we = 1;
ADDR_KEY6:
- begin
- key6_we = 1;
- end
+ key6_we = 1;
ADDR_KEY7:
- begin
- key7_we = 1;
- end
+ key7_we = 1;
ADDR_BLOCK0:
- begin
- block0_we = 1;
- end
+ block0_we = 1;
ADDR_BLOCK1:
- begin
- block1_we = 1;
- end
+ block1_we = 1;
ADDR_BLOCK2:
- begin
- block2_we = 1;
- end
+ block2_we = 1;
ADDR_BLOCK3:
- begin
- block3_we = 1;
- end
+ block3_we = 1;
default:
begin
@@ -479,112 +425,69 @@ module aes(
else
begin
case (address)
- // Read operations.
ADDR_NAME0:
- begin
- tmp_read_data = CORE_NAME0;
- end
+ tmp_read_data = CORE_NAME0;
ADDR_NAME1:
- begin
- tmp_read_data = CORE_NAME1;
- end
+ tmp_read_data = CORE_NAME1;
ADDR_VERSION:
- begin
- tmp_read_data = CORE_VERSION;
- end
+ tmp_read_data = CORE_VERSION;
ADDR_CTRL:
- begin
- tmp_read_data = {28'h0000000, keylen_reg, encdec_reg,
+ tmp_read_data = {28'h0000000, keylen_reg, encdec_reg,
next_reg, init_reg};
- end
ADDR_STATUS:
- begin
- tmp_read_data = {29'h00000000, error_reg, valid_reg, ready_reg};
- end
+ tmp_read_data = {29'h00000000, error_reg, valid_reg, ready_reg};
ADDR_KEY0:
- begin
- tmp_read_data = key0_reg;
- end
+ tmp_read_data = key0_reg;
ADDR_KEY1:
- begin
- tmp_read_data = key1_reg;
- end
+ tmp_read_data = key1_reg;
ADDR_KEY2:
- begin
- tmp_read_data = key2_reg;
- end
+ tmp_read_data = key2_reg;
ADDR_KEY3:
- begin
- tmp_read_data = key3_reg;
- end
+ tmp_read_data = key3_reg;
ADDR_KEY4:
- begin
- tmp_read_data = key4_reg;
- end
+ tmp_read_data = key4_reg;
ADDR_KEY5:
- begin
- tmp_read_data = key5_reg;
- end
+ tmp_read_data = key5_reg;
ADDR_KEY6:
- begin
- tmp_read_data = key6_reg;
- end
+ tmp_read_data = key6_reg;
ADDR_KEY7:
- begin
- tmp_read_data = key7_reg;
- end
+ tmp_read_data = key7_reg;
ADDR_BLOCK0:
- begin
- tmp_read_data = block0_reg;
- end
+ tmp_read_data = block0_reg;
ADDR_BLOCK1:
- begin
- tmp_read_data = block1_reg;
- end
+ tmp_read_data = block1_reg;
ADDR_BLOCK2:
- begin
- tmp_read_data = block2_reg;
- end
+ tmp_read_data = block2_reg;
ADDR_BLOCK3:
- begin
- tmp_read_data = block3_reg;
- end
+ tmp_read_data = block3_reg;
ADDR_RESULT0:
- begin
- tmp_read_data = result_reg[127 : 96];
- end
+ tmp_read_data = result_reg[127 : 96];
ADDR_RESULT1:
- begin
- tmp_read_data = result_reg[95 : 64];
- end
+ tmp_read_data = result_reg[95 : 64];
ADDR_RESULT2:
- begin
- tmp_read_data = result_reg[63 : 32];
- end
+ tmp_read_data = result_reg[63 : 32];
ADDR_RESULT3:
- begin
- tmp_read_data = result_reg[31 : 0];
- end
+ tmp_read_data = result_reg[31 : 0];
default:
begin