From 891730d13b324fad916572a82f0bd610c5de9aad Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:06:24 +0000 Subject: Rename for conversion --- .../GitRepositories%2Fuser%2Fjs%2Ftoggle.trac | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.trac (limited to 'raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.trac') diff --git a/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.trac b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.trac new file mode 100644 index 0000000..5c7d4d2 --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.trac @@ -0,0 +1,30 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +

toggle

+ +

Introduction

+ +

This repo contains a simple deign that toggles an ouput pin. The toggle +is in sync with the given sys_clk, but the toggle circuit divides down +the clock. The divisor is build time defined.

+ +

The design is used in the Cryptech FPGA design to observe internal +clock frequencies.

+ +

Status

+ +

Has been simulated with Icarus Verilog.

+}}} + +[[RepositoryIndex(format=table,glob=user/js/toggle)]] + +|| Clone `https://git.cryptech.is/user/js/toggle.git` || -- cgit v1.2.3