From 13d0f55865f8b1b851ce1e84597b144c5fd41662 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Sun, 13 Sep 2020 23:15:43 +0000
Subject: GC

---
 .../GitRepositories%2Ftest%2Fnovena_base.trac      | 47 ----------------------
 1 file changed, 47 deletions(-)
 delete mode 100644 raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base.trac

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-{{{
-#!htmlcomment
-
-This page is maintained automatically by a script.  Don't modify this page by hand,
-your changes will just be overwritten the next time the script runs.  Talk to your
-Friendly Neighborhood Repository Maintainer if you need to change something here.
-
-}}}
-
-{{{
-#!html
-<h1>Cryptech Novena FPGA baseline</h1>
-
-<h2>Introduction</h2>
-
-<p>This repo contains the Novena FPGA baseline developed as part of the
-Cryptech project. The design contains a new FPGA top level, now clock
-implementation and reworked EIM interface.</p>
-
-<p>The main purpose of the baseline is to allow us to run the Cryptech
-cores and FPGA system with the general system clock and then interface
-to the EIM with the EIM burst clock.</p>
-
-<h2>Technical details</h2>
-
-<p>The design tries to be a clean top that is easy for others to work on
-and adapt to their needs. The top is stripped from ports not needed for
-the baseline. All clock and reset implementation is placed in a separate
-module. The EIM interface is in a separate module and then the rest of
-the system is in a third module.</p>
-
-<p>Internally the baseline contains an arbiter to connect cores with a
-32-bit memory like interface to the EIM. Finally there is SW to
-configure the EIM interface as well as talking to a test core in the
-FPGA.</p>
-
-<p>For information about the EIM clocking and the baseline HW and SW
-design, see the documentation.</p>
-
-<h2>Author</h2>
-
-<p>The baseline has been written by Pavel Shatov.</p>
-}}}
-
-[[RepositoryIndex(format=table,glob=test/novena_base)]]
-
-|| Clone `https://git.cryptech.is/test/novena_base.git` ||
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