From b092ffbcbe2c9398494f7dc9db6f0796971633e0 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:04:30 +0000 Subject: Import Cryptech wiki dump --- .../GitRepositories%2Fcore%2Frng%2Fvndecorrelator | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 raw-wiki-dump/GitRepositories%2Fcore%2Frng%2Fvndecorrelator (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Frng%2Fvndecorrelator') diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Frng%2Fvndecorrelator b/raw-wiki-dump/GitRepositories%2Fcore%2Frng%2Fvndecorrelator new file mode 100644 index 0000000..da72d9a --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Frng%2Fvndecorrelator @@ -0,0 +1,34 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +

vndecorrelator

+ +

A Verilog implementation of a von Neumann decorrelator.

+ +

This tiny module consumes pairs of bits and generates decorrelated +bits. Basically given a sequence of two bits, the decorrelator will:

+ +

0, 1: Emit 1 +1, 0: Emit 0 +0, 0: Emit nothing +1, 1: Emit nothing

+ +

The rate of bits emitted is thus at most half of the bitrate on the +input.

+ +

The module is synchronous, but bits may arrive a number of cycles +between eachother. The module will set the syn_out flag during one cycle +to signal that the value in data_out is a valid bit.

+}}} + +[[RepositoryIndex(format=table,glob=core/rng/vndecorrelator)]] + +|| Clone `https://git.cryptech.is/core/rng/vndecorrelator.git` || -- cgit v1.2.3