From 13d0f55865f8b1b851ce1e84597b144c5fd41662 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:15:43 +0000 Subject: GC --- .../GitRepositories%2Fcore%2Fmath%2Fmodexpa7.trac | 251 --------------------- 1 file changed, 251 deletions(-) delete mode 100644 raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexpa7.trac (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexpa7.trac') diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexpa7.trac b/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexpa7.trac deleted file mode 100644 index c112db2..0000000 --- a/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexpa7.trac +++ /dev/null @@ -1,251 +0,0 @@ -{{{ -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -}}} - -{{{ -#!html -

ModExpA7

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Core Description

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This core implements modular exponentiation using the Artix-7 FPGA found on CrypTech Alpha board. It can be used during RSA operations such as encryption/decryption and signing.

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Compile-Time Settings

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The core has two synthesis-time parameters:

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SYSTOLIC_ARRAY_POWERNUM_DSP
142
270
3126
4238
5462
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Given that Alpha board FPGA has 740 DSP slices, SYSTOLIC_ARRAY_POWER=5 is the largest possible setting. Note that if two cores are needed (eg. to do the two easier CRT exponentiations simultaneously), this parameter should be reduced to 4 to fit two cores into the device.

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API Specification

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The interface of the core is similar to other CrypTech cores. FMC memory map is split into two parts, the first part contains registers and looks like the following:

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OffsetRegister
0x0000NAME0
0x0004NAME1
0x0008VERSION
0x0020CONTROL
0x0024STATUS
0x0040MODE
0x0044MODULUS_BITS
0x0048EXPONENT_BITS
0x004CBUFFER_BITS
0x0050ARRAY_BITS
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The core has the following registers:

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The second part of the address space contains eight operand banks.

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Length of each bank (BANK_LENGTH) depends on the largest supported operand width: 0x80 bytes for 1024-bit core (OPERAND_ADDR_WIDTH = 5), 0x100 bytes for 2048-bit core (OPERAND_ADDR_WIDTH = 6), 0x200 bytes for 4096-bit core (OPERAND_ADDR_WIDTH = 7) and so on.

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The offset of the second part is 8 * BANK_LENGTH: 0x400 for 1024-bit core, 0x800 for 2048-bit core, 0x1000 for 4096-bit core and so on. The core has the following eight banks:

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OffsetBank
8 * BANK_LENGTHMODULUS
9 * BANK_LENGTHMESSAGE (BASE)
10 * BANK_LENGTHEXPONENT
11 * BANK_LENGTHRESULT
12 * BANK_LENGTHMODULUS_COEFF_OUT
13 * BANK_LENGTHMODULUS_COEFF_IN
14 * BANK_LENGTHMONTGOMERY_FACTOR_OUT
15 * BANK_LENGTHMONTGOMERY_FACTOR_IN
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MODULUS, MESSAGE and EXPONENT banks are read-write, the RESULT bank stores the result of the exponentiation and is read-only.

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After precomputation the modulus-dependent speed-up coefficient and the Montgomery factor are placed in "output" MODULUS_COEFF_OUT and MONTGOMERY_FACTOR_OUT banks, the two banks are read-only. Before exponentiation corresponding modulus-dependent coefficient and Montgomery factor must be placed in "input" MODULUS_COEFF_IN and MONTGOMERY_FACTOR_IN banks, they are read-write. This split input/output banks design allows precomputed quantities to be retrieved from the core and stored along with the key for later reuse. Note that each key requires three pairs of precomputed numbers: one for the public key and two for each of the secret key components.

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Implementation Details

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The top-level core module contains:

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The exponentiation module contains:

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The modular multiplier module contains:

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The systolic array of processing elements contains:

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Note, that the core is supplemented by a reference model written in C, that has extensive comments describing tricky corners of the underlying math.

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Vendor-specific Primitives

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CrypTech Alpha platform is based on the Xilinx Artix-7 200T FPGA, this core takes advantage of Xilinx-specific DSP slices to carry out math-intensive operations. All vendor-specific math primitives are placed under /rtl/pe/artix7/. The core also offers generic replacements under /rtl/pe/generic, they can be used for simulation with 3rd party tools, that are not aware of Xilinx-specific stuff. When porting to other architectures, only those three low-level modules need to be ported. Selection of vendor/generic primitives is done in modexpa7_primitive_switch.v. Note that if you change the latency of the processing element, the SYSTOLIC_PE_LATENCY setting in modexpa7_settings.v must be changed accordingly.

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