From 891730d13b324fad916572a82f0bd610c5de9aad Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:06:24 +0000 Subject: Rename for conversion --- raw-wiki-dump/GitRepositories%2Fcore%2Fhash%2Fsha1 | 308 --------------------- 1 file changed, 308 deletions(-) delete mode 100644 raw-wiki-dump/GitRepositories%2Fcore%2Fhash%2Fsha1 (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fhash%2Fsha1') diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fhash%2Fsha1 b/raw-wiki-dump/GitRepositories%2Fcore%2Fhash%2Fsha1 deleted file mode 100644 index d4c246d..0000000 --- a/raw-wiki-dump/GitRepositories%2Fcore%2Fhash%2Fsha1 +++ /dev/null @@ -1,308 +0,0 @@ -{{{ -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -}}} - -{{{ -#!html -

sha1

- -

Introduction

- -

Verilog implementation of the SHA-1 cryptgraphic hash function. The -functionality follows the specification in NIST FIPS 180-4.

- -

The sha1 design is divided into the following sections.

- - - -

The actual core consists of the following RTL files:

- - - -

The main core functionality is in the sha1_core file. The file -sha1_w_mem contains the message block memory W (see FIPS 180-4). -The top level entity is called sha1_core. The sha1_core module has wide -interfaces (512 bit block input, 160 bit digest). In order to make it -usable you probably want to wrap the core with a bus interface.

- -

The file sha1.v contains a top level wrapper that provides a simple -interface with 32-bit data access . This interface contains mesage block -and digest registers to allow a host to load the next block while the -current block is being processed.

- -

API

- -

The following list contains the address map for all registers -implemented by the sha1 top level wrapper:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
addressnameaccessdescription
0x00name0R"SHA1"
0x01name1R" "
0x02versionR"0.50"
0x08controlR/WControl of core. Bit 0: init, Bit 1: next
0x09statusR/WStatus of core. Bit 0: Ready, Bit 1: valid data
0x10block0R/Wdata block register
0x11block1R/Wdata block register
0x12block2R/Wdata block register
0x13block3R/Wdata block register
0x14block4R/Wdata block register
0x15block5R/Wdata block register
0x16block6R/Wdata block register
0x17block7R/Wdata block register
0x18block8R/Wdata block register
0x19block9R/Wdata block register
0x1ablock10R/Wdata block register
0x1bblock11R/Wdata block register
0x1cblock12R/Wdata block register
0x1dblock13R/Wdata block register
0x1eblock14R/Wdata block register
0x1fblock15R/Wdata block register
0x20digest0R/Wdigest register
0x21digest1R/Wdigest register
0x22digest2R/Wdigest register
0x23digest3R/Wdigest register
0x24digest4R/Wdigest register
- -

Implementation details

- -

The implementation is iterative with one cycle/round. The initialization -takes one cycle. The W memory is based around a sliding window of 16 -32-bit registers that are updated in sync with the round processing. The -total latency/message block is 82 cycles.

- -

All registers have asynchronous reset.

- -

The design has been implemented and tested on TerasIC DE0-Nano and C5G -FPGA boards.

- -

Status

- -

The design has been implemented and extensively been tested on TerasIC -DE0-Nano and C5G FPGA boards. The core has also been tested using SW -running on The Novena CPU talking to the core in the Xilinx Spartan-6 -FPGA.

- -

FPGA-results

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Altera Cyclone FPGAs

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Implementation results using Altera Quartus-II 13.1.

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Altera Cyclone IV E

- - - -

Altera Cyclone IV GX

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Altera Cyclone V

- - - -

Xilinx FPGAs

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Implementation results using ISE 14.7.

- -

* Xilinx Spartan-6 *

- - - -

TODO

- - -}}} - -[[RepositoryIndex(format=table,glob=core/hash/sha1)]] - -|| Clone `https://git.cryptech.is/core/hash/sha1.git` || -- cgit v1.2.3