From 891730d13b324fad916572a82f0bd610c5de9aad Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:06:24 +0000 Subject: Rename for conversion --- .../GitRepositories%2Fcore%2Fcomm%2Fuart.trac | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.trac (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.trac') diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.trac b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.trac new file mode 100644 index 0000000..6bfec8e --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.trac @@ -0,0 +1,26 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +

uart

+ +

A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.

+ +

This UART used to be in coretest, but has been moved out as a separate +project.

+ +

The current implementation supports the ability to set the bit rate as +well as number of data- and stop bits by writing to control addresses +via the control interface.

+}}} + +[[RepositoryIndex(format=table,glob=core/comm/uart)]] + +|| Clone `https://git.cryptech.is/core/comm/uart.git` || -- cgit v1.2.3