From 78b3ed35c726cf8ef0ec4c4e7753e6f4775b9001 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 9 May 2021 23:45:48 +0000 Subject: Finally get hanging text in lists mostly right --- pelican/content/InterconnectStandards.md | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'pelican/content/InterconnectStandards.md') diff --git a/pelican/content/InterconnectStandards.md b/pelican/content/InterconnectStandards.md index de0e81c..4ce1c83 100644 --- a/pelican/content/InterconnectStandards.md +++ b/pelican/content/InterconnectStandards.md @@ -28,29 +28,29 @@ system. Typical differences are: - Intelligence. Simple master-slave read/write access or DMA-transfers, - coherence support etc. - - point to point or point to multipoint. Basically bus based or switch + - point to point or point to multipoint. Basically bus based or switch fabric. + There are also non-technical differences: - Licensing and pricing. Does using a standard add monetary cost and - does using the standard infer restrictions in sharing, disclosure of source code? - - Market share. The market share is primarily interesting as basis for + - Market share. The market share is primarily interesting as basis for the availability of other cores that could be integrated. + ## Description of Standards ### AMBA @@ -64,26 +64,26 @@ AMBA currently contains four main interconnect types: - APB. A simple register read/write bus used to connect simpler - devices such as timers, IRQ handlers, slow serial I/O such as UARTS and GPIO interfaces. The peripherals are connected to a common bus with a single master. - - AHB. A more advanced bus based interconnect. Supports more complex + - AHB. A more advanced bus based interconnect. Supports more complex data transfers of up to 1 kByte data. Supports multiple masters. - - AXI. A switch fabric based interconnect that supports multiple + - AXI. A switch fabric based interconnect that supports multiple parallel transfers, multiple masters etc. - - ACE. A low latency interconnect that supports cache coherency to + - ACE. A low latency interconnect that supports cache coherency to allow the design of multicore, multiprocessor systems on-chip. + (There are also additional protocols in the AMBA specification for things like tracing etc.) @@ -98,19 +98,19 @@ different AMBA interconnect types. Pros: - Technically advanced and covers a wide range of system - requirements. + - A huge user base. - A huge selection of third party support in terms of tools as well as - cores. Most of these cores and tools are commercial and proprietary, closed source. + Cons: - Licensing. Would Cryptech need to get a license? @@ -153,11 +153,11 @@ Cons: - Low support from open and proprietary third party suppliers of tools - and cores. + ### CoreConnect CoreConnect [(8)](#fn8) is an interconnect standard initially developed by IBM. The standard is now used by several vendors, for example the -- cgit v1.2.3