From 88aaae1214226791cb1a862d02319a8470eea7e4 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 14 Feb 2021 21:23:06 +0000 Subject: Fix publication dates --- pelican/content/EDAToolchainSurvey.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'pelican/content/EDAToolchainSurvey.md') diff --git a/pelican/content/EDAToolchainSurvey.md b/pelican/content/EDAToolchainSurvey.md index e17f221..b54355a 100644 --- a/pelican/content/EDAToolchainSurvey.md +++ b/pelican/content/EDAToolchainSurvey.md @@ -1,5 +1,5 @@ -Date: 2016-12-15 22:43 Title: EDAToolchainSurvey +Date: 2016-12-15 22:43 The major issue is finding tools that allows a designer, user to verify that the RTL source code (in Verilog or VHDL) matches what is generated at the physical level. As part of the project we need to investigate the current status of open tools in the toolchain for implementation and verification of hardware. This includes RTL simulation, synthesis, place & route, netlist verification, timing analysis and configuration file generation and analysis. (This implies that the target is an FPGA.). If there are no open tools we need to find ways of verifying pre- and post-functionality to check that the black box tool does not alter (subvert) the design in ways not intended. -- cgit v1.2.3