From 5dc6a6966bb950cb19439e0dc57f77a630254f19 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 14 Feb 2021 20:26:34 +0000 Subject: Pelican-ize --- pelican/content/EDAToolchainSurvey.md | 3 +++ 1 file changed, 3 insertions(+) (limited to 'pelican/content/EDAToolchainSurvey.md') diff --git a/pelican/content/EDAToolchainSurvey.md b/pelican/content/EDAToolchainSurvey.md index ffd40e6..e17f221 100644 --- a/pelican/content/EDAToolchainSurvey.md +++ b/pelican/content/EDAToolchainSurvey.md @@ -1,3 +1,6 @@ +Date: 2016-12-15 22:43 +Title: EDAToolchainSurvey + The major issue is finding tools that allows a designer, user to verify that the RTL source code (in Verilog or VHDL) matches what is generated at the physical level. As part of the project we need to investigate the current status of open tools in the toolchain for implementation and verification of hardware. This includes RTL simulation, synthesis, place & route, netlist verification, timing analysis and configuration file generation and analysis. (This implies that the target is an FPGA.). If there are no open tools we need to find ways of verifying pre- and post-functionality to check that the black box tool does not alter (subvert) the design in ways not intended. The basic action flow is: -- cgit v1.2.3