From a1d28e4a70e8ddaec4968766149d61efb76448bc Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 14 Feb 2021 23:00:42 +0000 Subject: Yet more links --- pelican/content/AlphaBoardStrategy.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'pelican/content/AlphaBoardStrategy.md') diff --git a/pelican/content/AlphaBoardStrategy.md b/pelican/content/AlphaBoardStrategy.md index b6b07ae..df066e6 100644 --- a/pelican/content/AlphaBoardStrategy.md +++ b/pelican/content/AlphaBoardStrategy.md @@ -8,16 +8,16 @@ Develop a first, custom HSM board that can be used to support a first set of app * The use cases and requirements for the alpha board are specified on the [Dashboard](http://trac.cryptech.is/wiki/Dashboard). -* The basic blocks of the Alpha board is ["shown here"](Hardware). -* The ["BOM and component requirements"](AlphaBoardComponents). -* The detailed ["Alpha board functional drawing"](http://trac.cryptech.is/browser/doc/design/Alpha_board_drawing.pdf). +* The basic blocks of the Alpha board is [shown here](Hardware). +* The [BOM and component requirements](AlphaBoardComponents). +* The detailed [Alpha board functional drawing](http://trac.cryptech.is/browser/doc/design/Alpha_board_drawing.pdf). ## Plan 1. Choose FPGA and ARM (done) 2. Develop BOM, requirements and functional diagram (done-ish). -3. Develop complete ["schematics"](AlphaSchematics) (almost done). +3. Develop complete [schematics](AlphaSchematics) (almost done). 4. Develop dev-board ouorselves to connect chosen ARM to FPGA on Novena, to do some early development and testing in parallell with step 5. 5. Get professional designer to do many-layer PCB from schematics. 6. Manufacture a couple of boards (~10). @@ -28,7 +28,7 @@ Develop a first, custom HSM board that can be used to support a first set of app ## Way forward -We currently use the Novena as a dev-board. It has a ["Freescale i.MX6 CPU (ARM Cortex A9)"](http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&tab=Documentation_Tab&pspll=1&SelectedAsset=Documentation&ProdMetaId=PID/DC/i.MX6Q&fromPSP=true&assetLockedForNavigation=true&componentId=2&leftNavCode=1&pageSize=25&Documentation=Documentation/00610Ksd1nd%60%60Data%20Sheets&fpsp=1&linkline=Data%20Sheets), and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA. +We currently use the Novena as a dev-board. It has a [Freescale i.MX6 CPU (ARM Cortex A9)](http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&tab=Documentation_Tab&pspll=1&SelectedAsset=Documentation&ProdMetaId=PID/DC/i.MX6Q&fromPSP=true&assetLockedForNavigation=true&componentId=2&leftNavCode=1&pageSize=25&Documentation=Documentation/00610Ksd1nd%60%60Data%20Sheets&fpsp=1&linkline=Data%20Sheets), and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA. We want to over-size rather than under-size the FPGA on the Alpha board. The biggest FPGA from Xilinx/Altera that does not require tools with a commercial license that we've found is the ​Xilinx Artix-7 XC7A200T FBG484. -- cgit v1.2.3