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diff --git a/pelican/content/InterconnectStandards.md b/pelican/content/InterconnectStandards.md deleted file mode 100644 index a31da2c..0000000 --- a/pelican/content/InterconnectStandards.md +++ /dev/null @@ -1,323 +0,0 @@ -Title: InterconnectStandards -Author: trac -Date: 2016-12-15 22:44 - -# Comparison of On-Chip Bus Standards - -## Introduction -This document contains a brief summary of different on-chip bus -standards. The standards are described and compared based on license and -availability, technical specifications and general usage. - -The purpose of the document is to provide a basis for selecting the -primary bus standard for the Cryptech Open HSM project. - - -## Overview -System on Chip (SoC) designs require some sort of connectivity between -the different components (called cores or IP-cores, as in Intellectual -Property) that are placed onto the same die. - -There are several standards for on-chip interconnect, standards that -provide technical diversity that might be required by the -system. Typical differences are: - - -- Performance. The capacity as well as latency. - - - -- Intelligence. Simple master-slave read/write access or DMA-transfers, - coherence support etc. - - - -- point to point or point to multipoint. Basically bus based or switch - fabric. - - - -There are also non-technical differences: - - -- Licensing and pricing. Does using a standard add monetary cost and - does using the standard infer restrictions in sharing, disclosure of - source code? - - - -- Market share. The market share is primarily interesting as basis for - the availability of other cores that could be integrated. - - - -## Description of Standards - -### AMBA -AMBA (Advanced Microcontroller Bus Architecture) [(1)](#fn1), [(2)](#fn2) is a family of -interconnect standards from ARM Ltd. AMBA is widely used in systems -implemented in ASICs (for example mobile phone platforms), but are also -used in FPGAs. AMBA is for example used by the LEON [(3)](#fn3) processor -cores and subsystem GRLIB. - -AMBA currently contains four main interconnect types: - - -- APB. A simple register read/write bus used to connect simpler - devices such as timers, IRQ handlers, slow serial I/O such as UARTS - and GPIO interfaces. The peripherals are connected to a common bus - with a single master. - - - -- AHB. A more advanced bus based interconnect. Supports more complex - data transfers of up to 1 kByte data. Supports multiple masters. - - - -- AXI. A switch fabric based interconnect that supports multiple - parallel transfers, multiple masters etc. - - - -- ACE. A low latency interconnect that supports cache coherency to - allow the design of multicore, multiprocessor systems on-chip. - - -(There are also additional protocols in the AMBA specification for -things like tracing etc.) - -The license model for AMBA is _Open_ according to ARM. This seems to -mean that one can use AMBA to build a system. But at the same time, ARM -has intellectual properties to parts of the technology as well as -trademarks. For more information on ARM licensing, see [(4)](#fn4). - -The OpenCores project [(7)](#fn7) lists several cores as well as tools for -different AMBA interconnect types. - -Pros: - -- Technically advanced and covers a wide range of system - requirements. - - - -- A huge user base. - - - -- A huge selection of third party support in terms of tools as well as - cores. Most of these cores and tools are commercial and proprietary, - closed source. - - -Cons: - -- Licensing. Would Cryptech need to get a license? - - - -- Availability of open cores - - - - -### Avalon -Avalon [(5)](#fn5) is a proprietary switch fabric interconnect from Altera -corporation. It is used in systems developed using the Altera Nios-II -[(6)](#fn6) family of soft processor cores and related peripherals. - -According to Altera, the license for Avalon is open: "Avalon interfaces -are an open standard. No license or royalty is required to develop and -sell products that use, or are based on Avalon interfaces." - -As far as we can discern, Avalon is not generally used outside of Altera -based designs and not supported by a large group of third party -vendors. The OpenCores project lists only a few cores that uses Avalon -as interface standard. - -= -Pros: - -- Good technical features. - - - -- Easy integration in Nios-II based systems. - - -Cons: - -- Limited to Altera based FPGA designs. - - - -- Low support from open and proprietary third party suppliers of tools - and cores. - - - - -### CoreConnect -CoreConnect [(8)](#fn8) is an interconnect standard initially developed by -IBM. The standard is now used by several vendors, for example the -FPGA-vendor Xilinx[(9)](#fn9). - -Similarly to AMBA, CoreConnect contains several types of buses providing -simple peripheral access (DCR), high speed access for processor based -systems (OPB), as well as multicore solutions (PLB). - -The license for CoreConnect is granted by IBM [(10)](#fn10). The license seems to be -an AS IS-license, but contains a lot of other regulations. IBM holds a -number of patents related to CoreConnect (see the license agreement). - -Pros: - -- Good support on for systems implemented on Xilinx FPGAs. - - -Cons: - -- Low support by open cores and tools. -- License agreement. - - - -### OCP -The Open Core Protocol [(11)](#fn11) is a vendor neutral open interconnect standard -being developed by the EDA standards organisation Accellera [(12)](#fn12). The -standards was previously developed by the vendor organisation OCP-IP [(13)](#fn13), -but were transferred to Accellera in October 2013. - -Like AMBA, OCP contains a wide range of interconnect types from simple -register read/write access over a common bus to point to -point-interconnect and coherency support. - -There are quite a few commercial cores using OCP, but there seem to be -very few open cores using OCP. OpenCores only lists a few cores and -they are all bridges used to connect OCP to AMBA or Wishbone. - -The license for accessing the specification itself is an amended AS -IS-type license[(14)](#fn14). The license for the interconnect seems to be rather -open. - -Pros: - -- Good technical features. - - -Cons: - -- Not very common in use by open cores. - - - -### Wishbone -Wishbone [(15)](#fn15)[(16)](#fn16) (often written WISHBONE) is an open interconnect -standard developed by members of the OpenCore project as an alternative -to commercial solutions - primarily AMBA. - -Wishbone supports bus based as well as switch fabric interconnect -solutions of Wishbone cores. There are cores and tools to create CPU -based systems with buses and fabrics. Technically Wishbone is simpler -that AMBA and CoreConnect, but provides multimasters, point to point -switch fabrics, etc. - -There are tools available to generate Wishbone interfaces for a core as -well as creating a Wishbone connected system with different types of -interconnect solutions. - -The main use is related to the OpenRISC CPU core platform -[(17)](#fn17)[(18)](#fn18). OpenCores lists a huge selection of cores with Wishbone -support. The majority of these cores have LGPL and GPL licenses. There -are also third party commercial vendors that support Wishbone cores and -systems. - -The license for the Wishbone standard is public domain and dos not -impose any restrictions on usage in cores and systems. The -specification document itself is close to Creative Commons CC-BY. - -Pros: - -- Fairly good technical support. -- Good support from open tools and cores. -- Public domain license. - - -Cons: - -- Not as advanced. No good coherency support for example. - - - -## Conclusions -OF the different standards, only two standards are really interesting -for Cryptech - AMBA and Wishbone. - -From a technical point of view, selecting AMBA would be the proper -choice. AMBA provides all types of interconnect that a Cryptech -implementation might need. Also, building a Cryptech implementation -using third party cores (CPU cores for example) would be easier with -AMBA than the other standards. Wher AMBA falls short is the questions -related to licensing as well as the a bit less common support from open -cores and tools. - -Based on ease of licensing, openness and availability of open cores, -Wishbone is an easy choice. Wishbone would quite probably meet all -performance and functionality requirements a Cryptech implementation -might have. Integration with and support from commercial cores, tools -and vendors will however not be as good. Choosing Wishbone will quite -probably mean more work for the Cryptech project to deliver cores and -tools. And for the users of Cryptech Wishbone may also require more work -and thus reduce the interest Cryptech as a HSM solution. - - - -## References -1. https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture - -2. http://www.arm.com/products/system-ip/amba/amba-open-specifications.php - -3. https://en.wikipedia.org/wiki/LEON - -4. http://www.arm.com/products/system-ip/amba/index.php?tab=AMBA+Trademark+Guidelines - -5. http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - -6. http://www.altera.com/devices/processor/nios2/ni2-index.html - -7. http://opencores.org/ - -8. https://en.wikipedia.org/wiki/CoreConnect - -9. http://www.xilinx.com/products/intellectual-property/dr_pcentral_coreconnect.htm - -10. http://www.xilinx.com/ipcenter/doc/ibm_click_core_connect_license.pdf - -11. https://en.wikipedia.org/wiki/Open_Core_Protocol - -12. https://en.wikipedia.org/wiki/Accellera - -13. http://www.ocpip.org/ - -14. http://www.ocpip.org/license_signup.php - -15. http://opencores.org/opencores,wishbone - -16. https://en.wikipedia.org/wiki/Wishbone_(computer_bus) - -17. http://openrisc.net/ - -18. http://opencores.org/or1k/Main_Page - - -## Copyright and License - -This document has been written by Joachim Strömbergson. - -(c) 2014 SUNET - The Swedish University Network - -This document is licensed under a Creative Commons license (CC BY 3.0). -For more information, see: - -https://creativecommons.org/licenses/by/3.0/ |