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author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:04:30 +0000 |
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committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:04:30 +0000 |
commit | b092ffbcbe2c9398494f7dc9db6f0796971633e0 (patch) | |
tree | 6fabf690f1ebf485a9fea9af5298e44ad2a59a3e /raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle | |
parent | 9d927e49d9c10fc16c6dfa4a2a96cdb6216e4e2b (diff) |
Import Cryptech wiki dump
Diffstat (limited to 'raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle')
-rw-r--r-- | raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle new file mode 100644 index 0000000..5c7d4d2 --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle @@ -0,0 +1,30 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +<h1>toggle</h1> + +<h2>Introduction</h2> + +<p>This repo contains a simple deign that toggles an ouput pin. The toggle +is in sync with the given sys_clk, but the toggle circuit divides down +the clock. The divisor is build time defined.</p> + +<p>The design is used in the Cryptech FPGA design to observe internal +clock frequencies.</p> + +<h2>Status</h2> + +<p>Has been simulated with Icarus Verilog.</p> +}}} + +[[RepositoryIndex(format=table,glob=user/js/toggle)]] + +|| Clone `https://git.cryptech.is/user/js/toggle.git` || |