From b092ffbcbe2c9398494f7dc9db6f0796971633e0 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:04:30 +0000 Subject: Import Cryptech wiki dump --- ...positories%2Fuser%2Fshatov%2Fmodexpng_fpga_model | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model (limited to 'raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model') diff --git a/raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model b/raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model new file mode 100644 index 0000000..8309852 --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model @@ -0,0 +1,21 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +

modexpng_fpga_model

+ +

Math model of ModExpNG IP core. The model mimics how an FPGA does modular exponentiation.

+ +

First use the scripts from the vector/ folder to generate and format a keypair vector, then edit the DUMP_* switches in modexpng_fpga_model.py to dump the desired internal values. The FORCE_OVERFLOW setting artificially forces the virtually neven seen internal interim overflow situation and allows its handler to be tested. You can also un-comment the _#c.dump_banks()_ line and move it anywhere within _sign_using_crt()_ and/or _sign_without_crt()_ to dump the contents of entire core's memory.

+}}} + +[[RepositoryIndex(format=table,glob=user/shatov/modexpng_fpga_model)]] + +|| Clone `https://git.cryptech.is/user/shatov/modexpng_fpga_model.git` || -- cgit v1.2.3