From 13d0f55865f8b1b851ce1e84597b144c5fd41662 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:15:43 +0000 Subject: GC --- ...ories%2Fuser%2Fshatov%2Fmodexpng_fpga_model.trac | 21 --------------------- 1 file changed, 21 deletions(-) delete mode 100644 raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model.trac (limited to 'raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model.trac') diff --git a/raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model.trac b/raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model.trac deleted file mode 100644 index 8309852..0000000 --- a/raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model.trac +++ /dev/null @@ -1,21 +0,0 @@ -{{{ -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -}}} - -{{{ -#!html -

modexpng_fpga_model

- -

Math model of ModExpNG IP core. The model mimics how an FPGA does modular exponentiation.

- -

First use the scripts from the vector/ folder to generate and format a keypair vector, then edit the DUMP_* switches in modexpng_fpga_model.py to dump the desired internal values. The FORCE_OVERFLOW setting artificially forces the virtually neven seen internal interim overflow situation and allows its handler to be tested. You can also un-comment the _#c.dump_banks()_ line and move it anywhere within _sign_using_crt()_ and/or _sign_without_crt()_ to dump the contents of entire core's memory.

-}}} - -[[RepositoryIndex(format=table,glob=user/shatov/modexpng_fpga_model)]] - -|| Clone `https://git.cryptech.is/user/shatov/modexpng_fpga_model.git` || -- cgit v1.2.3