From 13d0f55865f8b1b851ce1e84597b144c5fd41662 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Sun, 13 Sep 2020 23:15:43 +0000
Subject: GC

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-```
-#!htmlcomment
-
-This page is maintained automatically by a script.  Don't modify this page by hand,
-your changes will just be overwritten the next time the script runs.  Talk to your
-Friendly Neighborhood Repository Maintainer if you need to change something here.
-
-```
-
-```
-#!html
-<h1>sha512</h1>
-
-<p>Verilog implementation of the SHA-512 hash function. This implementation
-complies with the functionality in NIST FIPS 180-4. The supports the
-SHA-512 variants SHA-512/224, SHA-512/256, SHA-384 and SHA-512.</p>
-
-<h2>Implementation details</h2>
-
-<p>The core uses a sliding window with 16 64-bit registers for the W
-memory. The top level wrapper contains flag control registers for init
-and next that automatically resets. This means that the flags must be
-set for every block to be processed.</p>
-
-<h2>Status</h2>
-
-<p><strong><em>(2014-04-05)</em></strong></p>
-
-<p>RTL for the core and top is completed Testbenches for core and top
-completed. All single block and dual block test cases works. Results
-after building the complete design for Altera Cyclone V GX:</p>
-
-<ul>
-<li>2919 ALMs</li>
-<li>3609 Registers</li>
-<li>77 MHz max clock frequency</li>
-</ul>
-
-<p><strong><em>(2014-03-24)</em></strong></p>
-
-<p>Core works for the SHA-512 mode case. Added top level wrapper and built
-the design for Altera Cyclone V GX:</p>
-
-<ul>
-<li>2923 ALMs</li>
-<li>3609 Registers</li>
-<li>80 MHz max clock frequency</li>
-</ul>
-
-<p><strong><em>(2014-02-23)</em></strong></p>
-
-<p>Initial version. Based on the SHA-256 core. Nothing really to see yet.</p>
-```
-
-[[RepositoryIndex(format=table,glob=core/hash/sha512)]]
-
-| Clone `https://git.cryptech.is/core/hash/sha512.git` |
-|---|
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