From 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Sun, 13 Sep 2020 23:10:21 +0000
Subject: Initial conversion pass

---
 .../GitRepositories%2Fcore%2Fcomm%2Fuart.md        | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md

(limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md')

diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md
new file mode 100644
index 0000000..7a2532d
--- /dev/null
+++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md
@@ -0,0 +1,27 @@
+```
+#!htmlcomment
+
+This page is maintained automatically by a script.  Don't modify this page by hand,
+your changes will just be overwritten the next time the script runs.  Talk to your
+Friendly Neighborhood Repository Maintainer if you need to change something here.
+
+```
+
+```
+#!html
+<h1>uart</h1>
+
+<p>A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.</p>
+
+<p>This UART used to be in coretest, but has been moved out as a separate
+project.</p>
+
+<p>The current implementation supports the ability to set the bit rate as
+well as number of data- and stop bits by writing to control addresses
+via the control interface.</p>
+```
+
+[[RepositoryIndex(format=table,glob=core/comm/uart)]]
+
+| Clone `https://git.cryptech.is/core/comm/uart.git` |
+|---|
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