From 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Sun, 13 Sep 2020 23:10:21 +0000
Subject: Initial conversion pass

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+```
+#!htmlcomment
+
+This page is maintained automatically by a script.  Don't modify this page by hand,
+your changes will just be overwritten the next time the script runs.  Talk to your
+Friendly Neighborhood Repository Maintainer if you need to change something here.
+
+```
+
+```
+#!html
+<h1>chacha</h1>
+
+<p>Verilog 2001 implementation of the ChaCha stream cipher.</p>
+
+<h2>Functionality</h2>
+
+<p>This core implements ChaCha with support for 128 and 256 bit keys. The
+number of rounds can be set from two to 32 rounds in steps of two. The
+default number of rounds is eight.</p>
+
+<p>The core contains an internal 64-bit block counter that is automatically
+updated for each data block.</p>
+
+<h2>Performance</h2>
+
+<p>Each quarterround takes one cycle which means that the mininum latency
+will be 4*rounds. When the core is functionally correct we will add two
+more version with 2 and 4 parallel quarterrounds respectively. The four
+quarterounds version will achieve 1 cycle/round.</p>
+
+<h2>Implementation</h2>
+
+<p>Implementation results using the Altera Quartus 13 design tool.</p>
+
+<h3>Cyclone IV GX</h3>
+
+<ul>
+<li>6233 LEs</li>
+<li>3677 registers</li>
+<li>56.1 MHz</li>
+<li>11 cycles latency</li>
+<li>2.6 Gbps performance.</li>
+</ul>
+
+<h3>Cyclone V GX</h3>
+
+<ul>
+<li>2631 ALMs for logic</li>
+<li>3677 registers</li>
+<li>54.3 MHz</li>
+<li>11 cycles latency</li>
+<li>2.5 Gbps performance.</li>
+</ul>
+
+<h2>Status</h2>
+
+<p>(2014-09-03)
+- Added a new port in the core to allow setting of the initial value of
+the counter. The top level wrapper currently sets this value to a
+constant zero.</p>
+
+<ul>
+<li>Added the ChaCha core to Cryptech.</li>
+</ul>
+```
+
+[[RepositoryIndex(format=table,glob=core/cipher/chacha)]]
+
+| Clone `https://git.cryptech.is/core/cipher/chacha.git` |
+|---|
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