From b092ffbcbe2c9398494f7dc9db6f0796971633e0 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 13 Sep 2020 23:04:30 +0000 Subject: Import Cryptech wiki dump --- .../GitRepositories%2Fcore%2Fcipher%2Faes | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 raw-wiki-dump/GitRepositories%2Fcore%2Fcipher%2Faes (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fcipher%2Faes') diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fcipher%2Faes b/raw-wiki-dump/GitRepositories%2Fcore%2Fcipher%2Faes new file mode 100644 index 0000000..b46c33c --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fcipher%2Faes @@ -0,0 +1,90 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +

aes_speed

+ +

Speed optimized Verilog implementation of the symmetric block cipher AES +(Advanced Encryption Standard) as specified in the NIST document FIPS +197.

+ +

This core is modified version of the Cryptech AES core. Note that the +name of the core modules are identical to that core. The purpose of this +is to allow a drop-in replacement in Cryptech designs.

+ +

Status

+ +

Second round of optimizations done. The core has been implemented in +FPGA and tested in real HW.

+ +

Introduction

+ +

This implementation supports 128 and 256 bit keys. The +implementation is iterative and process one 128 block at a time.

+ +

The encipher and decipher block processing datapaths are separated and +basically self contained given access to a set of round keys and a +block. This makes it possible to hard wire either encipher or decipher +and allow the build tools to optimize away the other functionality which +will reduce the size to about 50%. For cipher modes such as CTR, GCM +decryption in the AES core will never be used and thus the decipher +block processing can be removed.

+ +

The core has been equipped with 16 S-boxes for encipher and 16 Inverse +S-boxes for decipher. This allows the core to perform the SubBytes and +InverseSubBytes operations in the AES round functions in one cycle.

+ +

The key expansion does not share S-boxes with the encipher datapath, so +the total number of S-boxes is 40.

+ +

Performance comparison

+ +

Number of cycles for the old Cryptech AES core:

+ + + +

Number of cycles for the Cryptech AES speed core:

+ + + +

Note that these latency numbers are after key expansion. The given key +must be expanded byt asserting the init control bit and wait for ready +to be asserted. Key expansion takes about 10 to 14 cycles.

+ +

Implementation comparison

+ +

Implementation results for Xilinx Artix7-t200.

+ +

Old Cryptech AES core:

+ + + +

Cryptec AES speed core:

+ + +}}} + +[[RepositoryIndex(format=table,glob=core/cipher/aes)]] + +|| Clone `https://git.cryptech.is/core/cipher/aes.git` || -- cgit v1.2.3