From a1d28e4a70e8ddaec4968766149d61efb76448bc Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 14 Feb 2021 23:00:42 +0000 Subject: Yet more links --- pelican/content/AlphaBoardComponents.md | 4 ++-- pelican/content/AlphaBoardStrategy.md | 10 +++++----- pelican/content/CoretestHashesC5G.md | 2 +- pelican/content/CoretestHashesNovena.md | 4 ++-- pelican/content/Dashboard.md | 2 +- pelican/content/EDAToolchainSurvey.md | 8 ++++---- pelican/content/OpenCryptoChip.md | 10 +++++----- pelican/content/RandomnessTesting.md | 2 +- pelican/content/RelatedWork.md | 4 ++-- pelican/content/UsingSTLink.md | 2 +- trac2md.py | 30 +++++++++++++++--------------- 11 files changed, 39 insertions(+), 39 deletions(-) diff --git a/pelican/content/AlphaBoardComponents.md b/pelican/content/AlphaBoardComponents.md index 3dfd1fa..ee9da4a 100644 --- a/pelican/content/AlphaBoardComponents.md +++ b/pelican/content/AlphaBoardComponents.md @@ -104,7 +104,7 @@ The FPGA pad layout should be compatible with the Xilinx Artix-7 FGG484 used by -* Suggestion for FPGA config memory is ["M25P128 EEPROM from Micron"](http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb), with a jumper controlling the write-enable pin. +* Suggestion for FPGA config memory is [M25P128 EEPROM from Micron](http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb), with a jumper controlling the write-enable pin. * Suggested MUX is the Quad 2-channel Analog Switch: ON Semi. MC14551B [http://www.onsemi.com/pub_link/Collateral/MC14551B-D.PDF](http://www.onsemi.com/pub_link/Collateral/MC14551B-D.PDF) @@ -188,7 +188,7 @@ The main CPU is a ST Microelectronics STM32F429BIT6 Cortex-M4 based MCU running ### External RAM The STM32 CPU supports two separate SDRAM banks. We use both of them with as big SDRAM chips we can find for each bank. The chip used is 64 MByte for a total of 128 Mbyte RAM. -* ["ISSI IS45S32160F 64 MByte SDRAM with 32 bit data interface"](http://www.issi.com/WW/pdf/42-45R-S-32160F.pdf) +* [ISSI IS45S32160F 64 MByte SDRAM with 32 bit data interface](http://www.issi.com/WW/pdf/42-45R-S-32160F.pdf) diff --git a/pelican/content/AlphaBoardStrategy.md b/pelican/content/AlphaBoardStrategy.md index b6b07ae..df066e6 100644 --- a/pelican/content/AlphaBoardStrategy.md +++ b/pelican/content/AlphaBoardStrategy.md @@ -8,16 +8,16 @@ Develop a first, custom HSM board that can be used to support a first set of app * The use cases and requirements for the alpha board are specified on the [Dashboard](http://trac.cryptech.is/wiki/Dashboard). -* The basic blocks of the Alpha board is ["shown here"](Hardware). -* The ["BOM and component requirements"](AlphaBoardComponents). -* The detailed ["Alpha board functional drawing"](http://trac.cryptech.is/browser/doc/design/Alpha_board_drawing.pdf). +* The basic blocks of the Alpha board is [shown here](Hardware). +* The [BOM and component requirements](AlphaBoardComponents). +* The detailed [Alpha board functional drawing](http://trac.cryptech.is/browser/doc/design/Alpha_board_drawing.pdf). ## Plan 1. Choose FPGA and ARM (done) 2. Develop BOM, requirements and functional diagram (done-ish). -3. Develop complete ["schematics"](AlphaSchematics) (almost done). +3. Develop complete [schematics](AlphaSchematics) (almost done). 4. Develop dev-board ouorselves to connect chosen ARM to FPGA on Novena, to do some early development and testing in parallell with step 5. 5. Get professional designer to do many-layer PCB from schematics. 6. Manufacture a couple of boards (~10). @@ -28,7 +28,7 @@ Develop a first, custom HSM board that can be used to support a first set of app ## Way forward -We currently use the Novena as a dev-board. It has a ["Freescale i.MX6 CPU (ARM Cortex A9)"](http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&tab=Documentation_Tab&pspll=1&SelectedAsset=Documentation&ProdMetaId=PID/DC/i.MX6Q&fromPSP=true&assetLockedForNavigation=true&componentId=2&leftNavCode=1&pageSize=25&Documentation=Documentation/00610Ksd1nd%60%60Data%20Sheets&fpsp=1&linkline=Data%20Sheets), and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA. +We currently use the Novena as a dev-board. It has a [Freescale i.MX6 CPU (ARM Cortex A9)](http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&tab=Documentation_Tab&pspll=1&SelectedAsset=Documentation&ProdMetaId=PID/DC/i.MX6Q&fromPSP=true&assetLockedForNavigation=true&componentId=2&leftNavCode=1&pageSize=25&Documentation=Documentation/00610Ksd1nd%60%60Data%20Sheets&fpsp=1&linkline=Data%20Sheets), and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA. We want to over-size rather than under-size the FPGA on the Alpha board. The biggest FPGA from Xilinx/Altera that does not require tools with a commercial license that we've found is the ​Xilinx Artix-7 XC7A200T FBG484. diff --git a/pelican/content/CoretestHashesC5G.md b/pelican/content/CoretestHashesC5G.md index ff381df..da4e70c 100644 --- a/pelican/content/CoretestHashesC5G.md +++ b/pelican/content/CoretestHashesC5G.md @@ -230,7 +230,7 @@ or more submodules. - Navigate to test_coretest_hashes/cores/sha256/src/rtl and add the files sha256, sha256_core, - sha256_k_constants, sha256_w_mem. Do **NOT** add the file wb_sha256. This file contains an alternative top level wrapper to the one in sha256.v that instead provides a ["WISHBONE"](http://opencores.org/opencores,wishbone) interface. This interface is not used in the coretest_hashes design. + sha256_k_constants, sha256_w_mem. Do **NOT** add the file wb_sha256. This file contains an alternative top level wrapper to the one in sha256.v that instead provides a [WISHBONE](http://opencores.org/opencores,wishbone) interface. This interface is not used in the coretest_hashes design. - Finally navigate to test_coretest_hashes/cores/uart/src/rtl and add uart, uart_core. diff --git a/pelican/content/CoretestHashesNovena.md b/pelican/content/CoretestHashesNovena.md index dac8435..f99c1d2 100644 --- a/pelican/content/CoretestHashesNovena.md +++ b/pelican/content/CoretestHashesNovena.md @@ -28,7 +28,7 @@ iface eth0 inet dhcp * The specific CPU on the Novena is the Freescale i.MX6 MCIMX6Q5EYM12AC device. A quad core, ARM A9 device running at 1.2 GHz. * The specific FPGA on the Novena is the Xilinx Spartan-6 XC6SLX45-3CSG324C device. -* Here are ["the schematics for the Novena PVT2 board"](http://bunniefoo.com/novena/pvt2_release/novena_pvt2.PDF). +* Here are [the schematics for the Novena PVT2 board](http://bunniefoo.com/novena/pvt2_release/novena_pvt2.PDF). @@ -115,7 +115,7 @@ On the page [http://www.xilinx.com/products/design-tools/ise-design-suite/ise-we You do not need to go through the HostID dance, just say Do It. You will then receive a certificate in email (not an X.509 certificate) which you will be able to use. Then start the ISE Webpack by issuing the command `ise`. Go to the Help menu and `Manage Licenses`. Use the resulting new License Manager window to install the .lic file. This process is complex and flakey. -Here is a more detailed description of ["installing ISE in Ubuntu."](http://www.armadeus.com/wiki/index.php?title=ISE_WebPack_installation_on_Linux) +Here is a more detailed description of [installing ISE in Ubuntu.](http://www.armadeus.com/wiki/index.php?title=ISE_WebPack_installation_on_Linux) Platforms on which at least one person has done this succesfully: diff --git a/pelican/content/Dashboard.md b/pelican/content/Dashboard.md index d8a8884..931b102 100644 --- a/pelican/content/Dashboard.md +++ b/pelican/content/Dashboard.md @@ -82,7 +82,7 @@ Date: 2016-12-15 22:44 | Component | Status | Repository | Comment | |---|---|---|---| -| KEY WRAP | Done | | Key wrapping mode. Will be used for key storage. See ["rfc 3394"](https://tools.ietf.org/html/rfc3394). #17 | +| KEY WRAP | Done | | Key wrapping mode. Will be used for key storage. See [rfc 3394](https://tools.ietf.org/html/rfc3394). #17 | | GCM | Not started | | Galois Counter Mode. AEAD cipher. | | CTR and CBC | Not started | | Basic block cipher modes. | diff --git a/pelican/content/EDAToolchainSurvey.md b/pelican/content/EDAToolchainSurvey.md index b54355a..cdb1e4d 100644 --- a/pelican/content/EDAToolchainSurvey.md +++ b/pelican/content/EDAToolchainSurvey.md @@ -13,7 +13,7 @@ The basic action flow is: Some tools and frameworks worth investigating are: -* ["OpTiMSoC"](http://www.optimsoc.org/index.html) - An open System on Chip (SoC) framework built around the OpenRISC CPU. -* ["Icarus Verilog"](http://iverilog.icarus.com/) - An open Verilog event driven simulator that supports Verilog 2001, 2005 and SystemVerilog. -* ["gEDA"](http://www.geda-project.org/) - A project that aims at developing GNU based EDA tools. -* ["gplEDA"](http://www.gpleda.org/) - A collection of GPL licensed EDA tools. Points to gEDA. +* [OpTiMSoC](http://www.optimsoc.org/index.html) - An open System on Chip (SoC) framework built around the OpenRISC CPU. +* [Icarus Verilog](http://iverilog.icarus.com/) - An open Verilog event driven simulator that supports Verilog 2001, 2005 and SystemVerilog. +* [gEDA](http://www.geda-project.org/) - A project that aims at developing GNU based EDA tools. +* [gplEDA](http://www.gpleda.org/) - A collection of GPL licensed EDA tools. Points to gEDA. diff --git a/pelican/content/OpenCryptoChip.md b/pelican/content/OpenCryptoChip.md index ac91cf2..397e14e 100644 --- a/pelican/content/OpenCryptoChip.md +++ b/pelican/content/OpenCryptoChip.md @@ -91,8 +91,8 @@ As a proof of concept, to validate as much as possible the assurance of the tool # Ongoing Development -* ["SUNET is sponsoring the first two development steps"](SunetInitialDevelopment) currently being done. -* [" Investigation and planning of a TRNG with entropy sources"](TRNGDevelopment) +* [SUNET is sponsoring the first two development steps](SunetInitialDevelopment) currently being done. +* [ Investigation and planning of a TRNG with entropy sources](TRNGDevelopment) * [Investigation of possible EDA tools and ways to do open and assured HW development"](EDAToolchainSurvey") * [Collection about side-channel attacks and detection, mitigation methods"](SideChannel") @@ -114,7 +114,7 @@ As a proof of concept, to validate as much as possible the assurance of the tool * TerasIC C5G Cyclone 5 GX Starter Kit. Includes an Altera C5GX FPGA. This board is used for core, subsystem development and verification. Info, documentation and ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830 -Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](CoretestHashesC5G). +Here is a writeup on how to [setup and run coretest_hashes on the C5G board](CoretestHashesC5G). * TerasIC DE0-Nano board. This tiny, USB powered board is used for core development and verification. Info, documentation, resources, ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593 @@ -128,7 +128,7 @@ Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](C * Research * Select -* ["On-chip Interconnect Standards"](InterconnectStandards) to use. +* [On-chip Interconnect Standards](InterconnectStandards) to use. ## Methods and Validation @@ -190,4 +190,4 @@ Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](C # Future Development -The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible ["ASIC Implementations"](ASICImplementations). +The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible [ASIC Implementations](ASICImplementations). diff --git a/pelican/content/RandomnessTesting.md b/pelican/content/RandomnessTesting.md index 085ad76..3b2752f 100644 --- a/pelican/content/RandomnessTesting.md +++ b/pelican/content/RandomnessTesting.md @@ -48,7 +48,7 @@ There are a number of things to keep in mind when using `dieharder`, especially ### Installation -The ["Dieharder home page"](http://www.phy.duke.edu/~rgb/General/dieharder.php) provides the source code as well as documentation. Dieharder is also available via package systems in Linux (apt-get install dieharder) and by brew for OSX. +The [Dieharder home page](http://www.phy.duke.edu/~rgb/General/dieharder.php) provides the source code as well as documentation. Dieharder is also available via package systems in Linux (apt-get install dieharder) and by brew for OSX. ## The FIPS140-2 Test Suite `rngtest` from `rng-tools` diff --git a/pelican/content/RelatedWork.md b/pelican/content/RelatedWork.md index 92c97d3..688585d 100644 --- a/pelican/content/RelatedWork.md +++ b/pelican/content/RelatedWork.md @@ -14,8 +14,8 @@ other than TPM to do RSA calculations." ## SoftHSM -- ["SoftHSM"](https://www.opendnssec.org/softhsm/) - part of OpenDNSSEC -- ["Possum"](http://wiki.cacert.org/Possum) - an earlier attempt att an Open Source HSM. +- [SoftHSM](https://www.opendnssec.org/softhsm/) - part of OpenDNSSEC +- [Possum](http://wiki.cacert.org/Possum) - an earlier attempt att an Open Source HSM. diff --git a/pelican/content/UsingSTLink.md b/pelican/content/UsingSTLink.md index 93a420b..ba1219b 100644 --- a/pelican/content/UsingSTLink.md +++ b/pelican/content/UsingSTLink.md @@ -4,7 +4,7 @@ Modified: 2019-01-24 14:37 # Using ST-LINK -ST-LINK is STM's implementation of the [ Serial Wire Debug (SWD)](https://developer.arm.com/products/architecture/cpu-architecture/debug-visibility-and-trace/coresight-architecture/serial-wire-debug ) protocol. +ST-LINK is STM's implementation of the [Serial Wire Debug (SWD)](https://developer.arm.com/products/architecture/cpu-architecture/debug-visibility-and-trace/coresight-architecture/serial-wire-debug) protocol. Think of it as JTAG if you're more comfortable with that. ## Getting an ST-LINK programmer diff --git a/trac2md.py b/trac2md.py index 0804608..38038f3 100755 --- a/trac2md.py +++ b/trac2md.py @@ -70,19 +70,25 @@ def convert_headers(line): return line +def make_mdlink(text): + for sep in "| ": + if sep in text: + parts = text.split(sep, 1) + break + else: + parts = [text] + parts = [p.strip() for p in parts] + if parts[-1].startswith('"') and parts[-1].endswith('"'): + parts[-1] = parts[-1][1:-1] + return "[{}]({})".format(parts[-1], parts[0]) + + def convert_wikilinks_1(line): ''' Convert wikiformat links ''' m = wikilink_1_pattern.search(line) if m: - text = m.group(1) or m.group(2) - for sep in "| ": - if sep in text: - parts = text.split(sep, 1) - break - else: - parts = [text] - mdlink = "[{}]({})".format(parts[-1], parts[0]) + mdlink = make_mdlink(m.group(1) or m.group(2)) line = line.replace(m.group(0), mdlink) return line @@ -95,13 +101,7 @@ def convert_wikilinks_2(line): if text.lower() == "pageoutline": mdlink = "" else: - for sep in "| ": - if sep in text: - parts = text.split(sep, 1) - break - else: - parts = [text] - mdlink = "[{}]({})".format(parts[-1], parts[0]) + mdlink = make_mdlink(text) line = line.replace(m.group(0), mdlink) return line -- cgit v1.2.3