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diff --git a/markdown/AlphaBoardComponents.md b/markdown/AlphaBoardComponents.md index ba8ba53..20b2ca5 100644 --- a/markdown/AlphaBoardComponents.md +++ b/markdown/AlphaBoardComponents.md @@ -1,17 +1,25 @@ # CrypTech Alpha Board BOM and PCB design requirement sketch -This document contains a list of component level description and requirements for the Crypteh Alpha board.[[BR]] -The document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed.[[BR]] +This document contains a list of component level description and requirements for the Crypteh Alpha board. + +The document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed. + The block diagram for the Alpha board can be seen at: [wiki:Hardware] -The Alpha board basically consists of three major sub systems:[[BR]] -1. **The FPGA Sub System**[[BR]] - Used to implement CrypTech crypto/security cores accessible by the CPU as coprocessors.[[BR]] +The Alpha board basically consists of three major sub systems: + +1. **The FPGA Sub System** + + Used to implement CrypTech crypto/security cores accessible by the CPU as coprocessors. + + +2. **The CPU Sub System** -2. **The CPU Sub System**[[BR]] Talks to host systems and handles incoming commands. Basically implements the application interface. - Controls the FPGA Sub System. The CPU Sub System is heavily inspired/based on the CPU parts of the Novena and the iMX6 Rex boards.[[BR]] + Controls the FPGA Sub System. The CPU Sub System is heavily inspired/based on the CPU parts of the Novena and the iMX6 Rex boards. + + +3. **The Tamper Detect Sub System** -3. **The Tamper Detect Sub System**[[BR]] Responsible for implementing tamper detection and control/alarm as a separate functionality from the CPU. On the Alpha board this system is fairly simplistic. But we want to at least have a minor MCU that can run independently on battery power and control the Master Key Memory (MKM). detect external events and generate @@ -37,8 +45,12 @@ Joachim Strömbergson, Fredrik Thulin ### FPGA The board should be equipped with a Xilinx Artix-7 200T FPGA device, more specifically XC7A200T FBG484 speed grade -3. -* [Xilinx Artix-7 XC7A200T FBG484.][[BR]](http://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) -* [Product family overview][[BR]](http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf) +* [Xilinx Artix-7 XC7A200T FBG484.](http://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) + + + +* [Product family overview](http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf) + The FPGA pad layout should be compatible with the Xilinx Artix-7 FGG484 used by XC7A100T and XC7A75T. @@ -114,7 +126,8 @@ Suggested components for the MKM and the switch: * Memory: Microchip serial SRAM. 23A640, 8 kByte, 8-TSSOP or 8-SOIC -[http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf][[BR]](http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf][[BR]) +[http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf](http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf) + * Quad 2-channel Analog Switch: ON Semi. MC14551B @@ -184,8 +197,10 @@ The STM32 CPU supports two separate SDRAM banks. We use both of them with as big * Suggested chip: Microchip MCP79411 or MCP79412 connected to the CPU via I2C. - [http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411][[BR]](http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411][[BR]) - [http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf][[BR]](http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf][[BR]) + [http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411](http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411) + + [http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf](http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf) + This chip requires an external 32 kHz crystal. * Note: these chips contain per chip unique IDs as well as small EEPROM memory that can be memory protected. |