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author | Rob Austein <sra@hactrn.net> | 2021-07-09 22:46:41 +0000 |
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committer | Rob Austein <sra@hactrn.net> | 2021-07-09 22:46:41 +0000 |
commit | 019a6cd5cfa533b53346d0c38f939198f214667d (patch) | |
tree | d32abd2cdb84dee991086e37bcbf8575b2d8bed3 /pelican/content/RoughV1.md | |
parent | d5b501c4046fbdc2354607c12f9f8230159e6135 (diff) |
Run conversion with updated toolset
Diffstat (limited to 'pelican/content/RoughV1.md')
-rw-r--r-- | pelican/content/RoughV1.md | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/pelican/content/RoughV1.md b/pelican/content/RoughV1.md index c6bb597..1700e73 100644 --- a/pelican/content/RoughV1.md +++ b/pelican/content/RoughV1.md @@ -24,17 +24,13 @@ source out of the can. for v.2 (or whatever) we would move it down to the FPGA Verilog. ## FPGA Overview -![HW_sketch_v0001.png]({attach}RoughV1/HW_sketch_v0001.png) - - - - +![HW_sketch_v0001.png]({attach}/RoughV1/HW_sketch_v0001.png) +<br/> +<br/> ## Sketch of TRNG Chain -![HW_RNG.png]({attach}RoughV1/HW_RNG.png) - - - - +![HW_RNG.png]({attach}/RoughV1/HW_RNG.png) +<br/> +<br/> ## Off-FPGA |