From 8eea37e61e919819e6ef51d8a1c1bd04cfd0892a Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sun, 22 May 2016 14:21:03 +0300 Subject: Initial commit of code, that initializes the two on-board SDRAM chips. Includes simple memory test program. Note, that there turns out to be a bug in low-level HAL driver, so this commit includes corrected stm32f4xx_ll_fmc.c --- stm32-sdram.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 stm32-sdram.c (limited to 'stm32-sdram.c') diff --git a/stm32-sdram.c b/stm32-sdram.c new file mode 100644 index 0000000..16386e8 --- /dev/null +++ b/stm32-sdram.c @@ -0,0 +1,106 @@ +//----------------------------------------------------------------------------- +// stm32-sdram.c +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- +#include "stm32f4xx_hal.h" +#include "stm32-sdram.h" + + +//----------------------------------------------------------------------------- +int sdram_init(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2) +//----------------------------------------------------------------------------- +{ + HAL_StatusTypeDef ok; // status + FMC_SDRAM_CommandTypeDef cmd; // command + + + // + // enable clocking + // + cmd.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2; + cmd.AutoRefreshNumber = 1; + cmd.ModeRegisterDefinition = 0; + + HAL_Delay(1); + ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1); + if (ok != HAL_OK) return 0; + + // + // precharge all banks + // + cmd.CommandMode = FMC_SDRAM_CMD_PALL; + cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2; + cmd.AutoRefreshNumber = 1; + cmd.ModeRegisterDefinition = 0; + + HAL_Delay(1); + ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1); + if (ok != HAL_OK) return 0; + + + // + // send two auto-refresh commands in a row + // + cmd.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2; + cmd.AutoRefreshNumber = 1; + cmd.ModeRegisterDefinition = 0; + + ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1); + if (ok != HAL_OK) return 1; + + ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1); + if (ok != HAL_OK) return 1; + + + // + // load mode register + // + cmd.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2; + cmd.AutoRefreshNumber = 1; + cmd.ModeRegisterDefinition = SDRAM_MODEREG_BURST_LENGTH_1 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_2 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ; + + ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1); + if (ok != HAL_OK) return 1; + + + // + // set number of consequtive auto-refresh commands + // and program refresh rate + // + + // + // RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc + // + // RefreshCycles = 7.8125 us * 90 MHz = 703 + // + // According to the formula on p.1665 of the reference manual, + // we also need to subtract 20 from the value, so the target + // refresh rate is 703 - 20 = 683. + // + + ok = HAL_SDRAM_SetAutoRefreshNumber(sdram1, 8); + if (ok != HAL_OK) return 1; + + HAL_SDRAM_ProgramRefreshRate(sdram1, 683); + if (ok != HAL_OK) return 1; + + + // done + return 1; +} + + +//----------------------------------------------------------------------------- +// End-of-File +//----------------------------------------------------------------------------- -- cgit v1.2.3