From af78b5570d2229631b287915c25ae3021e9f6982 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov" Date: Thu, 27 Aug 2015 00:30:26 +0400 Subject: Initial revision of FMC arbiter for Novena's on-board FPGA. --- src/tb/tb_clkmgr_new.v | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 src/tb/tb_clkmgr_new.v (limited to 'src/tb/tb_clkmgr_new.v') diff --git a/src/tb/tb_clkmgr_new.v b/src/tb/tb_clkmgr_new.v new file mode 100644 index 0000000..75d281d --- /dev/null +++ b/src/tb/tb_clkmgr_new.v @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps + +module tb_clkmgr_new; + + + // + // Inputs + // + reg gclk = 1'b0; + reg gclk_stop; + wire gclk_p = (gclk & ~gclk_stop); + wire gclk_n = ~(gclk & ~gclk_stop); + reg reset_mcu_b; + + + + // + // Outputs + // + wire sys_clk; + wire sys_rst; + + + // + // UUT + // + novena_clkmgr_new # + ( + .CLK_OUT_MUL (4), // 200 MHz + .CLK_OUT_DIV (1) // + ) + uut + ( + .gclk_p (gclk_p), + .gclk_n (gclk_n), + + .reset_mcu_b (reset_mcu_b), + + .sys_clk (sys_clk), + .sys_rst (sys_rst) + ); + + + // + // Clock (50 MHz) + // + always #10 gclk = ~gclk; + + + // + // Script + // + initial begin + // + reset_mcu_b = 0; // reset active + gclk_stop = 0; // gclk running + // + #500; + // + reset_mcu_b = 1; // clear reset + // + #1000; + // + gclk_stop = 1; // try to stop gclk + #1000; + gclk_stop = 0; // enable gclk again + // + #1000; + // + reset_mcu_b = 0; // try to activate reset + #1000; + reset_mcu_b = 1; // clear reset again + // + end + +endmodule + -- cgit v1.2.3