Math model of ModExpNG IP core. The model mimics how an FPGA does modular exponentiation.
First use the scripts from the vector/ folder to generate and format a keypair vector, then edit the DUMP_* switches in modexpng_fpga_model.py to dump the desired internal values. The FORCE_OVERFLOW setting artificially forces the virtually neven seen internal interim overflow situation and allows its handler to be tested. You can also un-comment the #c.dump_banks() line and move it anywhere within sign_using_crt() and/or sign_without_crt() to dump the contents of entire core's memory.
