rtl/modexpng_sdp_36k_x32_x16_wrapper.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

module modexpng_sdp_36k_x32_x16_wrapper
(
    clk, clk_bus,
    
    ena, wea,
    addra, dina,
    
    enb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                     clk;
    input                                     clk_bus;
    
    input                                     ena;
    input                                     wea;
    input  [BANK_ADDR_W + OP_ADDR_W     -1:0] addra;
    input  [              WORD_W        -1:0] dina;
    
    input                                     enb;
    input  [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addrb;
    output [              BUS_DATA_W    -1:0] doutb;

    
    //
    // BRAM_SDP_MACRO
    //
    BRAM_SDP_MACRO #
    (
        .DEVICE                 ("7SERIES"),
        
        .BRAM_SIZE              ("36Kb"),
        
        .WRITE_WIDTH            (WORD_W),
        .READ_WIDTH             (BUS_DATA_W),
        
        .DO_REG                 (0),
        .WRITE_MODE             ("READ_FIRST"),
        
        .SRVAL                  (72'h000000000000000000),
        .INIT                   (72'h000000000000000000),

        .INIT_FILE              ("NONE"),
        .SIM_COLLISION_CHECK    ("NONE")
    )
    BRAM_SDP_MACRO_inst
    (
        .RST        (1'b0),
    
        .WRCLK      (clk),
        .WREN       (ena),
        .WE         ({2{wea}}),
        .WRADDR     (addra),
        .DI         (dina),
        
        .RDCLK      (clk_bus),
        .RDEN       (enb),
        .REGCE      (1'b0),
        .RDADDR     (addrb),
        .DO         (doutb)
    );
    
endmodule