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module modexpng_mmm_pad
(
clk, rst_n,
fsm_state,
load_xy_addr_lsb,
pad_x_rd_addr, pad_y_rd_addr,
pad_x_rd_ena, pad_y_rd_ena,
pad_x_rd_dout, pad_y_rd_dout,
load_x_din, load_y_din
);
//
// Includes
//
`include "modexpng_parameters.vh"
//`include "modexpng_parameters_x8.vh"
`include "modexpng_mmm_fsm.vh"
//
// Parameters
//
parameter INDEX_WIDTH = 6;
//
// Ports
//
input clk;
input rst_n;
input [FSM_STATE_WIDTH-1:0] fsm_state;
input [INDEX_WIDTH-1:0] load_xy_addr_lsb;
input [WORD_WIDTH-1:0] load_x_din;
input [WORD_WIDTH-1:0] load_y_din;
input [INDEX_WIDTH-1:0] pad_x_rd_addr;
input [INDEX_WIDTH-1:0] pad_y_rd_addr;
input pad_x_rd_ena;
input pad_y_rd_ena;
output [WORD_WIDTH-1:0] pad_x_rd_dout;
output [WORD_WIDTH-1:0] pad_y_rd_dout;
//
// Registers
//
reg [INDEX_WIDTH-1:0] pad_x_wr_addr;
reg [INDEX_WIDTH-1:0] pad_y_wr_addr;
reg pad_x_wr_ena;
reg pad_y_wr_ena;
reg [ WORD_WIDTH-1:0] pad_x_wr_din;
reg [ WORD_WIDTH-1:0] pad_y_wr_din;
bram_1wo_1ro_readfirst_ce #
(
.MEM_WIDTH (WORD_WIDTH),
.MEM_ADDR_BITS (INDEX_WIDTH)
)
pad_x
(
.clk (clk),
.a_addr (pad_x_wr_addr),
.a_en (pad_x_wr_ena),
.a_wr (pad_x_wr_ena),
.a_in (pad_x_wr_din),
.a_out (), // unused
.b_addr (pad_x_rd_addr),
.b_en (pad_x_rd_ena),
.b_out (pad_x_rd_dout)
);
bram_1wo_1ro_readfirst_ce #
(
.MEM_WIDTH (WORD_WIDTH),
.MEM_ADDR_BITS (INDEX_WIDTH)
)
pad_y
(
.clk (clk),
.a_addr (pad_y_wr_addr),
.a_en (pad_y_wr_ena),
.a_wr (pad_y_wr_ena),
.a_in (pad_y_wr_din),
.a_out (), // unused
.b_addr (pad_y_rd_addr),
.b_en (pad_y_rd_ena),
.b_out (pad_y_rd_dout)
);
always @(posedge clk)
//
case (fsm_state)
//
FSM_STATE_LOAD_T1T2_3: begin
pad_x_wr_addr <= load_xy_addr_lsb;
pad_y_wr_addr <= load_xy_addr_lsb;
end
//
default: begin
pad_x_wr_addr <= {INDEX_WIDTH{1'bX}};
pad_y_wr_addr <= {INDEX_WIDTH{1'bX}};
end
//
endcase
always @(posedge clk)
//
case (fsm_state)
//
FSM_STATE_LOAD_T1T2_3: begin
pad_x_wr_din <= load_x_din;
pad_y_wr_din <= load_y_din;
end
//
default: begin
pad_x_wr_din <= load_x_din;
pad_y_wr_din <= load_y_din;
end
//
endcase
always @(posedge clk or negedge rst_n)
//
if (!rst_n) begin
pad_x_wr_ena <= 1'b0;
pad_y_wr_ena <= 1'b0;
end else case (fsm_state)
//
FSM_STATE_LOAD_T1T2_3: begin
pad_x_wr_ena <= 1'b1;
pad_y_wr_ena <= 1'b1;
end
//
default: begin
pad_x_wr_ena <= 1'b0;
pad_y_wr_ena <= 1'b0;
end
//
endcase
endmodule
|
