1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
module modexpng_mmm_din_addr
(
clk, rst_n,
index_last,
fsm_state_next,
col_index_zero, col_index_next,
din_addr, din_bank, din_ena, din_reg_ena,
din_addr_cnt, din_addr_cnt_last,
din_addr_cnt_lower_prev, din_addr_cnt_upper_prev
);
//
// Includes
//
`include "modexpng_parameters.vh"
//`include "modexpng_parameters_x8.vh"
`include "modexpng_mmm_fsm.vh"
//
// Parameters
//
parameter INDEX_WIDTH = 6;
//
// Ports
//
input clk;
input rst_n;
input [ INDEX_WIDTH-1:0] index_last;
input [FSM_STATE_WIDTH-1:0] fsm_state_next;
input [ INDEX_WIDTH-4:0] col_index_zero;
input [ INDEX_WIDTH-4:0] col_index_next;
output [ INDEX_WIDTH-4:0] din_addr;
output [ 3-1:0] din_bank;
output [ 1-1:0] din_ena;
output [ 1-1:0] din_reg_ena;
output [ INDEX_WIDTH-1:0] din_addr_cnt;
output [ INDEX_WIDTH-1:0] din_addr_cnt_last;
output [ 3-1:0] din_addr_cnt_lower_prev;
output [ INDEX_WIDTH-4:0] din_addr_cnt_upper_prev;
//
// Address
//
reg [INDEX_WIDTH-1:0] din_addr_reg;
wire [INDEX_WIDTH-1:0] din_addr_zero = {INDEX_WIDTH{1'b0}};
reg [INDEX_WIDTH-1:0] din_addr_last;
wire [INDEX_WIDTH-1:0] din_addr_prev = (din_addr_reg == din_addr_zero) ? din_addr_last : din_addr_reg - 1'b1;
reg [INDEX_WIDTH-1:0] din_addr_cnt_reg;
wire [INDEX_WIDTH-1:0] din_addr_cnt_zero = {INDEX_WIDTH{1'b0}};
wire [INDEX_WIDTH-1:0] din_addr_cnt_next = din_addr_cnt_reg + 1'b1;
reg [INDEX_WIDTH-1:0] din_addr_cnt_last_reg;
wire [ 3-1:0] din_addr_cnt_lower = din_addr_cnt_reg[ 3-1:0];
wire [INDEX_WIDTH-4:0] din_addr_cnt_upper = din_addr_cnt_reg[INDEX_WIDTH-1:3];
reg [ 3-1:0] din_addr_cnt_lower_dly;
reg [INDEX_WIDTH-4:0] din_addr_cnt_upper_dly;
reg [ 3-1:0] din_bank_reg;
//
// Enables
//
reg din_ena_reg = 1'b0;
reg din_reg_ena_reg = 1'b0;
always @(posedge clk or negedge rst_n)
//
if (!rst_n)
din_ena_reg <= 1'b0;
else case (fsm_state_next)
//
FSM_STATE_MULT_SQUARE_COL_0_TRIG,
FSM_STATE_MULT_SQUARE_COL_N_TRIG,
FSM_STATE_MULT_SQUARE_COL_0_BUSY,
FSM_STATE_MULT_SQUARE_COL_N_BUSY:
din_ena_reg <= 1'b1;
//
default:
din_ena_reg <= 1'b0;
//
endcase
always @(posedge clk or negedge rst_n)
//
if (!rst_n)
din_reg_ena_reg <= 1'b0;
else
din_reg_ena_reg <= din_ena_reg;
//
// Address Mapping
//
assign din_addr = din_addr_reg[INDEX_WIDTH-1:3];
assign din_addr_cnt = din_addr_cnt_reg;
assign din_addr_cnt_last = din_addr_cnt_last_reg;
assign din_addr_cnt_lower_prev = din_addr_cnt_lower_dly;
assign din_addr_cnt_upper_prev = din_addr_cnt_upper_dly;
assign din_bank = din_bank_reg;
//
// Enable Mapping
//
assign din_ena = din_ena_reg;
assign din_reg_ena = din_reg_ena_reg;
//
// Delay
//
always @(posedge clk) begin
din_addr_cnt_lower_dly <= din_addr_cnt_lower;
din_addr_cnt_upper_dly <= din_addr_cnt_upper;
end
always @(posedge clk)
//
case (fsm_state_next)
//
FSM_STATE_MULT_SQUARE_COL_0_TRIG: begin
din_addr_reg <= {col_index_zero, {3{1'b0}}};
din_addr_last <= index_last;
din_addr_cnt_reg <= din_addr_cnt_zero;
din_addr_cnt_last_reg <= index_last;
end
//
FSM_STATE_MULT_SQUARE_COL_N_TRIG: begin
din_addr_reg <= {col_index_next, {3{1'b0}}};
din_addr_cnt_reg <= din_addr_cnt_zero;
end
//
FSM_STATE_MULT_SQUARE_COL_0_BUSY,
FSM_STATE_MULT_SQUARE_COL_N_BUSY: begin
din_addr_reg <= din_addr_prev;
din_addr_cnt_reg <= din_addr_cnt_next;
end
//
//default:
//
endcase
always @(posedge clk)
//
case (fsm_state_next)
//
FSM_STATE_MULT_SQUARE_COL_0_TRIG,
FSM_STATE_MULT_SQUARE_COL_N_TRIG,
FSM_STATE_MULT_SQUARE_COL_0_BUSY,
FSM_STATE_MULT_SQUARE_COL_N_BUSY:
din_bank_reg = BANK_XY_T1T2;
//
default:
din_bank_reg = BANK_XY_ANY;
//
endcase
endmodule
|
