module modexpng_uop_rom
(
    clk,
    addr,
    data
);

    `include "modexpng_parameters.vh"
    `include "modexpng_microcode.vh"

    input  wire 	              clk;
    input  wire [UOP_ADDR_W -1:0] addr;
    output reg  [UOP_W      -1:0] data;    

    always @(posedge clk)
        //
        case (addr)
            6'd00:      data <= {UOP_OPCODE_INPUT_TO_WIDE,    UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_N,        BANK_WIDE_N,    BANK_DNC         };
            6'd01:      data <= {UOP_OPCODE_INPUT_TO_WIDE,    UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_N,        BANK_WIDE_N,    BANK_DNC         };
            6'd02:      data <= {UOP_OPCODE_INPUT_TO_WIDE,    UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_X,        BANK_WIDE_A,    BANK_DNC         };
            6'd03:      data <= {UOP_OPCODE_INPUT_TO_WIDE,    UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_Y,        BANK_WIDE_A,    BANK_DNC         };
            6'd04:      data <= {UOP_OPCODE_INPUT_TO_WIDE,    UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_M,        BANK_WIDE_E,    BANK_DNC         };
            6'd05:      data <= {UOP_OPCODE_INPUT_TO_WIDE,    UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_M,        BANK_WIDE_E,    BANK_DNC         };

            6'd06:      data <= {UOP_OPCODE_INPUT_TO_NARROW,  UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_N_COEFF,  BANK_DNC,       BANK_NARROW_COEFF};
            6'd07:      data <= {UOP_OPCODE_INPUT_TO_NARROW,  UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_N_COEFF,  BANK_DNC,       BANK_NARROW_COEFF};
            6'd08:      data <= {UOP_OPCODE_INPUT_TO_NARROW,  UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_N_FACTOR, BANK_DNC,       BANK_NARROW_A    };
            6'd09:      data <= {UOP_OPCODE_INPUT_TO_NARROW,  UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_N_FACTOR, BANK_DNC,       BANK_NARROW_A    };
            6'd10:      data <= {UOP_OPCODE_INPUT_TO_NARROW,  UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_M,        BANK_DNC,       BANK_NARROW_E    };
            6'd11:      data <= {UOP_OPCODE_INPUT_TO_NARROW,  UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,    BANK_IN_1_M,        BANK_DNC,       BANK_NARROW_E    };
            
            6'd12:      data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N,   UOP_AUX_DNC, UOP_LADDER_11,  BANK_WIDE_A, BANK_NARROW_A,      BANK_WIDE_B,    BANK_NARROW_B    };
            
            default:    data <= {UOP_OPCODE_STOP,             UOP_CRT_DNC, UOP_NPQ_DNC, UOP_AUX_DNC, UOP_LADDER_DNC, UOP_SEL_DNC_ALL};
        endcase

endmodule