module modexpng_tdp_36k_x16_x32_wrapper ( clk, clk_bus, ena, wea, addra, dina, douta, enb, regceb, addrb, doutb ); // // Headers // `include "modexpng_parameters.vh" // // Ports // input clk; input clk_bus; input ena; input wea; input [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addra; input [ BUS_DATA_W -1:0] dina; output [ BUS_DATA_W -1:0] douta; input enb; input regceb; input [BANK_ADDR_W + OP_ADDR_W -1:0] addrb; output [ WORD_W -1:0] doutb; // // BRAM_TDP_MACRO // BRAM_TDP_MACRO # ( .DEVICE ("7SERIES"), .BRAM_SIZE ("36Kb"), .WRITE_WIDTH_A (BUS_DATA_W), .READ_WIDTH_A (BUS_DATA_W), .WRITE_WIDTH_B (WORD_W), .READ_WIDTH_B (WORD_W), .DOA_REG (0), .DOB_REG (1), .WRITE_MODE_A ("READ_FIRST"), .WRITE_MODE_B ("READ_FIRST"), .SRVAL_A (36'h000000000), .SRVAL_B (36'h000000000), .INIT_A (36'h000000000), .INIT_B (36'h000000000), .INIT_FILE ("NONE"), .SIM_COLLISION_CHECK ("NONE") ) BRAM_TDP_MACRO_inst ( .RSTA (1'b0), .RSTB (1'b0), .CLKA (clk_bus), .ENA (ena), .REGCEA (1'b0), .WEA ({4{wea}}), .ADDRA (addra), .DIA (dina), .DOA (douta), .CLKB (clk), .ENB (enb), .REGCEB (regceb), .WEB ({2{1'b0}}), .ADDRB (addrb), .DIB ({WORD_W{1'b0}}), .DOB (doutb) ); endmodule