module modexpng_storage_block ( clk, clk_bus, rst, wr_wide_xy_ena, wr_wide_xy_bank, wr_wide_xy_addr, wr_wide_x_din, wr_wide_y_din, wr_narrow_xy_ena, wr_narrow_xy_bank, wr_narrow_xy_addr, wr_narrow_x_din, wr_narrow_y_din, rd_wide_xy_ena, rd_wide_xy_ena_aux, rd_wide_xy_bank, rd_wide_xy_bank_aux, rd_wide_xy_addr, rd_wide_xy_addr_aux, rd_wide_x_dout, rd_wide_y_dout, rd_wide_x_dout_aux, rd_wide_y_dout_aux, rd_narrow_xy_ena, rd_narrow_xy_bank, rd_narrow_xy_addr, rd_narrow_x_dout, rd_narrow_y_dout, bus_cs, bus_we, bus_addr, bus_data_wr, bus_data_rd, in_1_en, in_1_addr, in_1_dout, in_2_en, in_2_addr, in_2_dout, out_en, out_we, out_addr, out_din ); // // Headers // `include "modexpng_parameters.vh" // // Ports // input clk; input clk_bus; input rst; input wr_wide_xy_ena; input [ BANK_ADDR_W -1:0] wr_wide_xy_bank; input [ OP_ADDR_W -1:0] wr_wide_xy_addr; input [ WORD_EXT_W -1:0] wr_wide_x_din; input [ WORD_EXT_W -1:0] wr_wide_y_din; input wr_narrow_xy_ena; input [ BANK_ADDR_W -1:0] wr_narrow_xy_bank; input [ OP_ADDR_W -1:0] wr_narrow_xy_addr; input [ WORD_EXT_W -1:0] wr_narrow_x_din; input [ WORD_EXT_W -1:0] wr_narrow_y_din; input rd_wide_xy_ena; input rd_wide_xy_ena_aux; input [ BANK_ADDR_W -1:0] rd_wide_xy_bank; input [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; input [ NUM_MULTS_HALF * OP_ADDR_W -1:0] rd_wide_xy_addr; input [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux; output [ NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_x_dout; output [ NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_y_dout; output [ WORD_EXT_W -1:0] rd_wide_x_dout_aux; output [ WORD_EXT_W -1:0] rd_wide_y_dout_aux; input rd_narrow_xy_ena; input [ BANK_ADDR_W -1:0] rd_narrow_xy_bank; input [ OP_ADDR_W -1:0] rd_narrow_xy_addr; output [ WORD_EXT_W -1:0] rd_narrow_x_dout; output [ WORD_EXT_W -1:0] rd_narrow_y_dout; input bus_cs; input bus_we; input [2 + BANK_ADDR_W + BUS_OP_ADDR_W -1:0] bus_addr; input [ BUS_DATA_W -1:0] bus_data_wr; output [ BUS_DATA_W -1:0] bus_data_rd; input in_1_en; input [ BANK_ADDR_W + OP_ADDR_W -1:0] in_1_addr; output [ WORD_W -1:0] in_1_dout; input in_2_en; input [ BANK_ADDR_W + OP_ADDR_W -1:0] in_2_addr; output [ WORD_W -1:0] in_2_dout; input out_en; input out_we; input [ BANK_ADDR_W + OP_ADDR_W -1:0] out_addr; input [ WORD_W -1:0] out_din; // // Internal Registers // reg rd_wide_xy_reg_ena = 1'b0; reg rd_wide_xy_reg_ena_aux = 1'b0; reg rd_narrow_xy_reg_ena = 1'b0; reg in_1_reg_en = 1'b0; reg in_2_reg_en = 1'b0; always @(posedge clk) // if (rst) begin rd_wide_xy_reg_ena <= 1'b0; rd_wide_xy_reg_ena_aux <= 1'b0; rd_narrow_xy_reg_ena <= 1'b0; in_1_reg_en <= 1'b0; in_2_reg_en <= 1'b0; end else begin rd_wide_xy_reg_ena <= rd_wide_xy_ena; rd_wide_xy_reg_ena_aux <= rd_wide_xy_ena_aux; rd_narrow_xy_reg_ena <= rd_narrow_xy_ena; in_1_reg_en <= in_1_en; in_2_reg_en <= in_2_en; end // // Helper Signals // wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_wide_xy_offset[0:NUM_MULTS_HALF-1]; wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_wide_xy_offset_aux; wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_narrow_xy_offset; wire [BANK_ADDR_W + OP_ADDR_W -1:0] wr_wide_xy_offset; wire [BANK_ADDR_W + OP_ADDR_W -1:0] wr_narrow_xy_offset; assign rd_wide_xy_offset_aux = {rd_wide_xy_bank_aux, rd_wide_xy_addr_aux}; assign rd_narrow_xy_offset = {rd_narrow_xy_bank, rd_narrow_xy_addr}; assign wr_wide_xy_offset = {wr_wide_xy_bank, wr_wide_xy_addr}; assign wr_narrow_xy_offset = {wr_narrow_xy_bank, wr_narrow_xy_addr}; // // "Wide" Storage // genvar z; generate for (z=0; z