From 72902f5b40ac695786f5103d2a5a456c6c7ee83f Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Mon, 21 Oct 2019 13:04:07 +0300
Subject: Redesigned the testbench. Core clock does not necessarily need to be
 twice faster than the bus clock now. It can be the same, or say four times
 faster.

---
 rtl/modexpng_dsp48e1.vh                        |   1 +
 rtl/modexpng_dsp_array_block.v                 |  84 ++++++++++-
 rtl/modexpng_dsp_slice_primitive.vh            |   9 ++
 rtl/modexpng_dsp_slice_wrapper.v               | 135 ------------------
 rtl/modexpng_dsp_slice_wrapper_generic.v       | 189 +++++++++++++++++++++++++
 rtl/modexpng_dsp_slice_wrapper_xilinx.v        | 135 ++++++++++++++++++
 rtl/modexpng_io_block.v                        |  19 ++-
 rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v |  66 +++++----
 rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v |  59 ++++----
 rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v |  43 ++++++
 rtl/modexpng_uop_rom.v                         |  20 +++
 11 files changed, 543 insertions(+), 217 deletions(-)
 create mode 100644 rtl/modexpng_dsp_slice_primitive.vh
 delete mode 100644 rtl/modexpng_dsp_slice_wrapper.v
 create mode 100644 rtl/modexpng_dsp_slice_wrapper_generic.v
 create mode 100644 rtl/modexpng_dsp_slice_wrapper_xilinx.v

(limited to 'rtl')

diff --git a/rtl/modexpng_dsp48e1.vh b/rtl/modexpng_dsp48e1.vh
index bc3d55c..410ad41 100644
--- a/rtl/modexpng_dsp48e1.vh
+++ b/rtl/modexpng_dsp48e1.vh
@@ -6,3 +6,4 @@ localparam DSP48E1_P_W       = 48;
 localparam DSP48E1_INMODE_W  = 5;
 localparam DSP48E1_OPMODE_W  = 7;
 localparam DSP48E1_ALUMODE_W = 4;
+
diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v
index 8c4e844..6b4ad3c 100644
--- a/rtl/modexpng_dsp_array_block.v
+++ b/rtl/modexpng_dsp_array_block.v
@@ -6,8 +6,9 @@ module modexpng_dsp_array_block
     a, b, p
 );
 
-    `include "modexpng_dsp48e1.vh"
     `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+    `include "modexpng_dsp_slice_primitive.vh"
 
     input                                            clk;
     
@@ -38,14 +39,87 @@ module modexpng_dsp_array_block
         ce_a2 <= ce_a1;
         ce_b1 <= ce_b0;
     end
-        
+    
+    ///
+    wire [46:0] p_debug_direct;
+    wire [17:0] casc_a_debug_direct;
+    wire [15:0] casc_b_debug_direct;
+    
+    wire [46:0] p_debug_cascade;
+
+    wire [46:0] p_ref_direct  = p[    0 +: MAC_W];
+    wire [46:0] p_ref_cascade = p[MAC_W +: MAC_W];
+    
+    modexpng_dsp_slice_wrapper_xilinx #
+    (
+        .AB_INPUT("DIRECT"),
+        .B_REG(2)
+    )
+    dsp_debug_direct
+    (
+        .clk            (clk),
+                
+        .ce_a1          (ce_a0),
+        .ce_b1          (ce_b0),
+        .ce_a2          (ce_a1),
+        .ce_b2          (ce_b1),
+        .ce_m           (ce_m),
+        .ce_p           (ce_p),
+        .ce_mode        (ce_mode),
+                
+        .a              (a[0 +: 18]),
+        .b              (b),
+        .p              (p_debug_direct),
+                
+        .inmode         ({DSP48E1_INMODE_W{1'b0}}),
+        .opmode         ({1'b0, mode_z[0], 1'b0, 2'b01, 2'b01}),
+        .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
+                
+        .casc_a_in      (WORD_EXT_ZERO),
+        .casc_b_in      (WORD_ZERO),
+                
+        .casc_a_out     (casc_a_debug_direct),
+        .casc_b_out     (casc_b_debug_direct)
+    );
+            
+    modexpng_dsp_slice_wrapper_xilinx #
+    (
+        .AB_INPUT("CASCADE"),
+        .B_REG(1)
+    )
+    dsp_debug_cascade
+    (
+        .clk            (clk),
+                
+        .ce_a1          (ce_a1),
+        .ce_b1          (1'b0),
+        .ce_a2          (ce_a2),
+        .ce_b2          (ce_b1),
+        .ce_m           (ce_m),
+        .ce_p           (ce_p),
+        .ce_mode        (ce_mode),
+                
+        .a              (a[0 +: 18]),
+        .b              (b),
+        .p              (p_debug_cascade),
+                
+        .inmode         ({DSP48E1_INMODE_W{1'b0}}),
+        .opmode         ({1'b0, mode_z[1], 1'b0, 2'b01, 2'b01}),
+        .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
+                
+        .casc_a_in      (casc_a_debug_direct),
+        .casc_b_in      (casc_b_debug_direct),
+                
+        .casc_a_out     (),
+        .casc_b_out     ()
+    );    
     
     genvar z;
     generate for (z=0; z<NUM_MULTS_HALF; z=z+1)
         //
         begin : gen_DSP48E1
             //        
-            modexpng_dsp_slice_wrapper #
+            `MODEXPNG_DSP_SLICE #
             (
                 .AB_INPUT("DIRECT"),
                 .B_REG(2)
@@ -77,7 +151,7 @@ module modexpng_dsp_array_block
                 .casc_b_out     (casc_b[z])
             );
             //
-            modexpng_dsp_slice_wrapper #
+            `MODEXPNG_DSP_SLICE #
             (
                 .AB_INPUT("CASCADE"),
                 .B_REG(1)
@@ -113,7 +187,7 @@ module modexpng_dsp_array_block
         //
     endgenerate
 
-    modexpng_dsp_slice_wrapper #
+    `MODEXPNG_DSP_SLICE #
     (
         .AB_INPUT("DIRECT"),
         .B_REG(2)
diff --git a/rtl/modexpng_dsp_slice_primitive.vh b/rtl/modexpng_dsp_slice_primitive.vh
new file mode 100644
index 0000000..02d9a5d
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_primitive.vh
@@ -0,0 +1,9 @@
+`ifndef MODEXPNG_ENABLE_DEBUG
+
+`define MODEXPNG_DSP_SLICE     modexpng_dsp_slice_wrapper_xilinx
+
+`else
+
+`define MODEXPNG_DSP_SLICE     modexpng_dsp_slice_wrapper_generic
+
+`endif
diff --git a/rtl/modexpng_dsp_slice_wrapper.v b/rtl/modexpng_dsp_slice_wrapper.v
deleted file mode 100644
index 3d13570..0000000
--- a/rtl/modexpng_dsp_slice_wrapper.v
+++ /dev/null
@@ -1,135 +0,0 @@
-module modexpng_dsp_slice_wrapper #
-(
-    AB_INPUT   = "DIRECT",
-    B_REG      = 2
-)
-(
-    clk,
-    ce_a1, ce_b1, ce_a2, ce_b2,
-    ce_m, ce_p, ce_mode,
-    a, b, p,
-    inmode, opmode, alumode,
-    casc_a_in,  casc_b_in,
-    casc_a_out, casc_b_out
-);
-
-    `include "modexpng_parameters.vh"
-    `include "modexpng_dsp48e1.vh"
-        
-    input                           clk;
-    input                           ce_a1;
-    input                           ce_b1;
-    input                           ce_a2;
-    input                           ce_b2;
-    input                           ce_m;
-    input                           ce_p;
-    input                           ce_mode;
-    input  [       WORD_EXT_W -1:0] a;
-    input  [           WORD_W -1:0] b;
-    output [            MAC_W -1:0] p;
-    input  [ DSP48E1_INMODE_W -1:0] inmode;
-    input  [ DSP48E1_OPMODE_W -1:0] opmode;
-    input  [DSP48E1_ALUMODE_W -1:0] alumode;
-    input  [       WORD_EXT_W -1:0] casc_a_in;
-    input  [           WORD_W -1:0] casc_b_in;
-    output [       WORD_EXT_W -1:0] casc_a_out;
-    output [           WORD_W -1:0] casc_b_out;
-    
-    wire [DSP48E1_A_W - WORD_EXT_W -1:0] casc_a_dummy;
-    wire [DSP48E1_B_W - WORD_W     -1:0] casc_b_dummy;
-    wire [DSP48E1_P_W - MAC_W      -1:0] p_dummy;
-
-    DSP48E1 #
-    (
-        .AREG                   (2),
-        .BREG                   (B_REG),
-        .CREG                   (0),
-        .DREG                   (0),
-        .ADREG                  (0),
-        .MREG                   (1),
-        .PREG                   (1),
-        .ACASCREG               (1),
-        .BCASCREG               (1),
-        .INMODEREG              (0),
-        .OPMODEREG              (1),
-        .ALUMODEREG             (0),
-        .CARRYINREG             (0),
-        .CARRYINSELREG          (0),
-
-        .A_INPUT                (AB_INPUT),
-        .B_INPUT                (AB_INPUT),
-
-        .USE_DPORT              ("FALSE"),
-        .USE_MULT               ("DYNAMIC"),
-        .USE_SIMD               ("ONE48"),
-
-        .MASK                   ({DSP48E1_P_W{1'b1}}),
-        .PATTERN                ({DSP48E1_P_W{1'b0}}),
-        .SEL_MASK               ("MASK"),
-        .SEL_PATTERN            ("PATTERN"),
-        
-        .USE_PATTERN_DETECT     ("NO_PATDET"),
-        .AUTORESET_PATDET       ("NO_RESET")
-    )
-    DSP48E1_inst
-    (
-        .CLK                (clk),
-    
-        .CEA1               (ce_a1),
-        .CEB1               (ce_b1),
-        .CEA2               (ce_a2),
-        .CEB2               (ce_b2),
-        .CEAD               (1'b0),
-        .CEC                (1'b0),
-        .CED                (1'b0),
-        .CEM                (ce_m),
-        .CEP                (ce_p),
-        .CEINMODE           (1'b0),
-        .CECTRL             (ce_mode),
-        .CEALUMODE          (1'b0),
-        .CECARRYIN          (1'b0),
-
-        .A                  ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
-        .B                  ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
-        .C                  ({DSP48E1_C_W{1'b0}}),
-        .D                  ({DSP48E1_D_W{1'b0}}),
-        .P                  ({p_dummy, p}),
-        
-        .INMODE             (inmode),
-        .OPMODE             (opmode),
-        .ALUMODE            (alumode),
-
-        .ACIN               ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, casc_a_in}),
-        .BCIN               ({{(DSP48E1_B_W-WORD_W){1'b0}}, casc_b_in}),
-        .ACOUT              ({casc_a_dummy, casc_a_out}),
-        .BCOUT              ({casc_b_dummy, casc_b_out}),
-        .PCIN               ({DSP48E1_P_W{1'b0}}),
-        .PCOUT              (),
-        .CARRYCASCIN        (1'b0),
-        .CARRYCASCOUT       (),
- 
-        .RSTA               (1'b0),
-        .RSTB               (1'b0),
-        .RSTC               (1'b0),
-        .RSTD               (1'b0),
-        .RSTM               (1'b0),
-        .RSTP               (1'b0),
-        .RSTINMODE          (1'b0),
-        .RSTCTRL            (1'b0),
-        .RSTALUMODE         (1'b0),
-        .RSTALLCARRYIN      (1'b0),
-
-        .UNDERFLOW          (),
-        .OVERFLOW           (),
-        .PATTERNDETECT      (),
-        .PATTERNBDETECT     (),
-
-        .CARRYIN            (1'b0),
-        .CARRYOUT           (),
-        .CARRYINSEL         (3'b000),
-
-        .MULTSIGNIN         (1'b0),
-        .MULTSIGNOUT        ()
- );
-
-endmodule
diff --git a/rtl/modexpng_dsp_slice_wrapper_generic.v b/rtl/modexpng_dsp_slice_wrapper_generic.v
new file mode 100644
index 0000000..7183d74
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_wrapper_generic.v
@@ -0,0 +1,189 @@
+module modexpng_dsp_slice_wrapper_generic #
+(
+    AB_INPUT   = "DIRECT",
+    B_REG      = 2
+)
+(
+    clk,
+    ce_a1, ce_b1, ce_a2, ce_b2,
+    ce_m, ce_p, ce_mode,
+    a, b, p,
+    inmode, opmode, alumode,
+    casc_a_in,  casc_b_in,
+    casc_a_out, casc_b_out
+);
+
+    `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+        
+    input                           clk;            //
+    input                           ce_a1;          //
+    input                           ce_b1;          //
+    input                           ce_a2;          //
+    input                           ce_b2;          //
+    input                           ce_m;           //
+    input                           ce_p;           //
+    input                           ce_mode;        //
+    input  [       WORD_EXT_W -1:0] a;              //
+    input  [           WORD_W -1:0] b;              //
+    output [            MAC_W -1:0] p;              //
+    input  [ DSP48E1_INMODE_W -1:0] inmode;         //
+    input  [ DSP48E1_OPMODE_W -1:0] opmode;         //
+    input  [DSP48E1_ALUMODE_W -1:0] alumode;        //
+    input  [       WORD_EXT_W -1:0] casc_a_in;      //
+    input  [           WORD_W -1:0] casc_b_in;      //
+    output [       WORD_EXT_W -1:0] casc_a_out;     //
+    output [           WORD_W -1:0] casc_b_out;     //
+    
+    //
+    // A Port
+    //
+    wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in;
+    reg  [WORD_EXT_W -1:0] a_reg1;
+    reg  [WORD_EXT_W -1:0] a_reg2;
+
+    assign casc_a_out = a_reg1;
+
+    always @(posedge clk) begin
+        if (ce_a1) a_reg1 <= a_mux;
+        if (ce_a2) a_reg2 <= a_reg1;
+    end
+    
+    //
+    // B Port
+    //
+    wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in;
+    reg  [WORD_W -1:0] b_reg1;
+    reg  [WORD_W -1:0] b_reg2;
+
+    assign casc_b_out = b_reg1;
+
+    always @(posedge clk) begin
+        if (ce_b1) b_reg1 <= b_mux;
+        if (ce_b2) b_reg2 <= B_REG == 2 ? b_reg1 : b_mux;
+    end
+
+    //
+    // OPMODE Port
+    //
+    reg [DSP48E1_OPMODE_W -1:0] opmode_reg;
+    
+    always @(posedge clk) begin
+        if (ce_mode) opmode_reg <= opmode;
+    end
+
+    //
+    // M, P
+    //
+    reg [MAC_W-1:0] m_reg;
+    reg [MAC_W-1:0] p_reg;
+    
+    wire [MAC_W-1:0] a_pad = {{MAC_W-WORD_EXT_W{1'b0}}, a_reg2};
+    wire [MAC_W-1:0] b_pad = {{MAC_W-WORD_W{1'b0}}, b_reg2};
+    wire [MAC_W-1:0] p_pad = opmode_reg[5] ? p_reg : {MAC_W{1'b0}};
+    
+    assign p = p_reg;
+    
+    always @(posedge clk) begin
+        if (ce_m) m_reg <= a_pad * b_pad;
+        if (ce_p) p_reg <= m_reg + p_pad;
+    end
+    
+
+    /*
+    DSP48E1 #
+    (
+        .AREG                   (2),
+        .BREG                   (B_REG),
+        .CREG                   (0),
+        .DREG                   (0),
+        .ADREG                  (0),
+        .MREG                   (1),
+        .PREG                   (1),
+        .ACASCREG               (1),
+        .BCASCREG               (1),
+        .INMODEREG              (0),
+        .OPMODEREG              (1),
+        .ALUMODEREG             (0),
+        .CARRYINREG             (0),
+        .CARRYINSELREG          (0),
+
+        .A_INPUT                (AB_INPUT),
+        .B_INPUT                (AB_INPUT),
+
+        .USE_DPORT              ("FALSE"),
+        .USE_MULT               ("DYNAMIC"),
+        .USE_SIMD               ("ONE48"),
+
+        .MASK                   ({DSP48E1_P_W{1'b1}}),
+        .PATTERN                ({DSP48E1_P_W{1'b0}}),
+        .SEL_MASK               ("MASK"),
+        .SEL_PATTERN            ("PATTERN"),
+        
+        .USE_PATTERN_DETECT     ("NO_PATDET"),
+        .AUTORESET_PATDET       ("NO_RESET")
+    )
+    DSP48E1_inst
+    (
+        .CLK                (clk),
+    
+        .CEA1               (ce_a1),
+        .CEB1               (ce_b1),
+        .CEA2               (ce_a2),
+        .CEB2               (ce_b2),
+        .CEAD               (1'b0),
+        .CEC                (1'b0),
+        .CED                (1'b0),
+        .CEM                (ce_m),
+        .CEP                (ce_p),
+        .CEINMODE           (1'b0),
+        .CECTRL             (ce_mode),
+        .CEALUMODE          (1'b0),
+        .CECARRYIN          (1'b0),
+
+        .A                  ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
+        .B                  ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
+        .C                  ({DSP48E1_C_W{1'b0}}),
+        .D                  ({DSP48E1_D_W{1'b0}}),
+        .P                  ({p_dummy, p}),
+        
+        .INMODE             (inmode),
+        .OPMODE             (opmode),
+        .ALUMODE            (alumode),
+
+        .ACIN               ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, casc_a_in}),
+        .BCIN               ({{(DSP48E1_B_W-WORD_W){1'b0}}, casc_b_in}),
+        .ACOUT              ({casc_a_dummy, casc_a_out}),
+        .BCOUT              ({casc_b_dummy, casc_b_out}),
+        .PCIN               ({DSP48E1_P_W{1'b0}}),
+        .PCOUT              (),
+        .CARRYCASCIN        (1'b0),
+        .CARRYCASCOUT       (),
+ 
+        .RSTA               (1'b0),
+        .RSTB               (1'b0),
+        .RSTC               (1'b0),
+        .RSTD               (1'b0),
+        .RSTM               (1'b0),
+        .RSTP               (1'b0),
+        .RSTINMODE          (1'b0),
+        .RSTCTRL            (1'b0),
+        .RSTALUMODE         (1'b0),
+        .RSTALLCARRYIN      (1'b0),
+
+        .UNDERFLOW          (),
+        .OVERFLOW           (),
+        .PATTERNDETECT      (),
+        .PATTERNBDETECT     (),
+
+        .CARRYIN            (1'b0),
+        .CARRYOUT           (),
+        .CARRYINSEL         (3'b000),
+
+        .MULTSIGNIN         (1'b0),
+        .MULTSIGNOUT        ()
+    );
+    */
+ 
+
+endmodule
diff --git a/rtl/modexpng_dsp_slice_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_wrapper_xilinx.v
new file mode 100644
index 0000000..9c1a60d
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_wrapper_xilinx.v
@@ -0,0 +1,135 @@
+module modexpng_dsp_slice_wrapper_xilinx #
+(
+    AB_INPUT   = "DIRECT",
+    B_REG      = 2
+)
+(
+    clk,
+    ce_a1, ce_b1, ce_a2, ce_b2,
+    ce_m, ce_p, ce_mode,
+    a, b, p,
+    inmode, opmode, alumode,
+    casc_a_in,  casc_b_in,
+    casc_a_out, casc_b_out
+);
+
+    `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+        
+    input                           clk;
+    input                           ce_a1;
+    input                           ce_b1;
+    input                           ce_a2;
+    input                           ce_b2;
+    input                           ce_m;
+    input                           ce_p;
+    input                           ce_mode;
+    input  [       WORD_EXT_W -1:0] a;
+    input  [           WORD_W -1:0] b;
+    output [            MAC_W -1:0] p;
+    input  [ DSP48E1_INMODE_W -1:0] inmode;
+    input  [ DSP48E1_OPMODE_W -1:0] opmode;
+    input  [DSP48E1_ALUMODE_W -1:0] alumode;
+    input  [       WORD_EXT_W -1:0] casc_a_in;
+    input  [           WORD_W -1:0] casc_b_in;
+    output [       WORD_EXT_W -1:0] casc_a_out;
+    output [           WORD_W -1:0] casc_b_out;
+    
+    wire [DSP48E1_A_W - WORD_EXT_W -1:0] casc_a_dummy;
+    wire [DSP48E1_B_W - WORD_W     -1:0] casc_b_dummy;
+    wire [DSP48E1_P_W - MAC_W      -1:0] p_dummy;
+
+    DSP48E1 #
+    (
+        .AREG                   (2),
+        .BREG                   (B_REG),
+        .CREG                   (0),
+        .DREG                   (0),
+        .ADREG                  (0),
+        .MREG                   (1),
+        .PREG                   (1),
+        .ACASCREG               (1),
+        .BCASCREG               (1),
+        .INMODEREG              (0),
+        .OPMODEREG              (1),
+        .ALUMODEREG             (0),
+        .CARRYINREG             (0),
+        .CARRYINSELREG          (0),
+
+        .A_INPUT                (AB_INPUT),
+        .B_INPUT                (AB_INPUT),
+
+        .USE_DPORT              ("FALSE"),
+        .USE_MULT               ("DYNAMIC"),
+        .USE_SIMD               ("ONE48"),
+
+        .MASK                   ({DSP48E1_P_W{1'b1}}),
+        .PATTERN                ({DSP48E1_P_W{1'b0}}),
+        .SEL_MASK               ("MASK"),
+        .SEL_PATTERN            ("PATTERN"),
+        
+        .USE_PATTERN_DETECT     ("NO_PATDET"),
+        .AUTORESET_PATDET       ("NO_RESET")
+    )
+    DSP48E1_inst
+    (
+        .CLK                (clk),
+    
+        .CEA1               (ce_a1),
+        .CEB1               (ce_b1),
+        .CEA2               (ce_a2),
+        .CEB2               (ce_b2),
+        .CEAD               (1'b0),
+        .CEC                (1'b0),
+        .CED                (1'b0),
+        .CEM                (ce_m),
+        .CEP                (ce_p),
+        .CEINMODE           (1'b0),
+        .CECTRL             (ce_mode),
+        .CEALUMODE          (1'b0),
+        .CECARRYIN          (1'b0),
+
+        .A                  ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
+        .B                  ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
+        .C                  ({DSP48E1_C_W{1'b0}}),
+        .D                  ({DSP48E1_D_W{1'b0}}),
+        .P                  ({p_dummy, p}),
+        
+        .INMODE             (inmode),
+        .OPMODE             (opmode),
+        .ALUMODE            (alumode),
+
+        .ACIN               ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, casc_a_in}),
+        .BCIN               ({{(DSP48E1_B_W-WORD_W){1'b0}}, casc_b_in}),
+        .ACOUT              ({casc_a_dummy, casc_a_out}),
+        .BCOUT              ({casc_b_dummy, casc_b_out}),
+        .PCIN               ({DSP48E1_P_W{1'b0}}),
+        .PCOUT              (),
+        .CARRYCASCIN        (1'b0),
+        .CARRYCASCOUT       (),
+ 
+        .RSTA               (1'b0),
+        .RSTB               (1'b0),
+        .RSTC               (1'b0),
+        .RSTD               (1'b0),
+        .RSTM               (1'b0),
+        .RSTP               (1'b0),
+        .RSTINMODE          (1'b0),
+        .RSTCTRL            (1'b0),
+        .RSTALUMODE         (1'b0),
+        .RSTALLCARRYIN      (1'b0),
+
+        .UNDERFLOW          (),
+        .OVERFLOW           (),
+        .PATTERNDETECT      (),
+        .PATTERNBDETECT     (),
+
+        .CARRYIN            (1'b0),
+        .CARRYOUT           (),
+        .CARRYINSEL         (3'b000),
+
+        .MULTSIGNIN         (1'b0),
+        .MULTSIGNOUT        ()
+    );
+
+endmodule
diff --git a/rtl/modexpng_io_block.v b/rtl/modexpng_io_block.v
index 06ce2b1..6d008aa 100644
--- a/rtl/modexpng_io_block.v
+++ b/rtl/modexpng_io_block.v
@@ -82,12 +82,12 @@ module modexpng_io_block
     wire [              BUS_DATA_W    -1:0] bus_data_rd_input_1;
     wire [              BUS_DATA_W    -1:0] bus_data_rd_output;
 
-    wire                                    bus_we_input_1 = bus_we && (bus_addr_msb == 2'd0);
-    wire                                    bus_we_input_2 = bus_we && (bus_addr_msb == 2'd1);
+    wire                                    bus_we_input_1 = bus_we && (bus_addr_msb == 2'd1);
+    wire                                    bus_we_input_2 = bus_we && (bus_addr_msb == 2'd2);
 
-    wire bus_cs_input_1 = bus_cs && (bus_addr_msb == 2'b00);
-    wire bus_cs_input_2 = bus_cs && (bus_addr_msb == 2'b01);
-    wire bus_cs_output  = bus_cs && (bus_addr_msb == 2'b10);
+    wire bus_cs_input_1 = bus_cs && (bus_addr_msb == 2'd1);
+    wire bus_cs_input_2 = bus_cs && (bus_addr_msb == 2'd2);
+    wire bus_cs_output  = bus_cs && (bus_addr_msb == 2'd3);
 
     /* INPUT_1 */
     `MODEXPNG_TDP_36K_X16_X32 bram_input_1
@@ -125,7 +125,6 @@ module modexpng_io_block
         .doutb      (in_2_dout)             //
     );
 
-
     /* OUTPUT */
     `MODEXPNG_SDP_36K_X32_X16 bram_output
     (
@@ -152,10 +151,10 @@ module modexpng_io_block
         //
         case (bus_addr_msb_dly)
             //
-            2'd0: bus_data_rd_mux = bus_data_rd_input_1;
-            2'd1: bus_data_rd_mux = 32'hDEADC0DE;
-            2'd2: bus_data_rd_mux = bus_data_rd_output;
-            2'd3: bus_data_rd_mux = 32'hDEADC0DE;
+            2'd0: bus_data_rd_mux = 32'hDEADC0DE;
+            2'd1: bus_data_rd_mux = bus_data_rd_input_1;
+            2'd2: bus_data_rd_mux = 32'hDEADC0DE;
+            2'd3: bus_data_rd_mux = bus_data_rd_output;
             //
         endcase
 
diff --git a/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v b/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v
index 034b00b..3797e41 100644
--- a/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v
+++ b/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v
@@ -34,42 +34,40 @@ module modexpng_sdp_36k_x16_x32_wrapper_generic
 
     
     //
-    // BRAM_SDP_MACRO
+    // Memory
     //
-    BRAM_SDP_MACRO #
-    (
-        .DEVICE                 ("7SERIES"),
-        
-        .BRAM_SIZE              ("36Kb"),
-        
-        .WRITE_WIDTH            (BUS_DATA_W),
-        .READ_WIDTH             (WORD_W),
-        
-        .DO_REG                 (1),
-        .WRITE_MODE             ("READ_FIRST"),
-        
-        .SRVAL                  (72'h000000000000000000),
-        .INIT                   (72'h000000000000000000),
-
-        .INIT_FILE              ("NONE"),
-        .SIM_COLLISION_CHECK    ("NONE")
-    )
-    BRAM_SDP_MACRO_inst
-    (
-        .RST        (1'b0),
+    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
+   
+    //
+    // Write Port
+    //
+    always @(posedge clk_bus)
+        //
+        if (ena && wea)
+            mem[addra] <= dina;
+            
+    //
+    // Read Port
+    //
+    reg [WORD_W -1:0] doutb_reg1;
+    reg [WORD_W -1:0] doutb_reg2;
+    
+    assign doutb = doutb_reg2;
+    
+    wire [BUS_DATA_W -1:0] mem_addrb = mem[addrb[BANK_ADDR_W + OP_ADDR_W -1:1]];
+    
+    wire [    WORD_W -1:0] mem_addrb_msb = mem_addrb[ BUS_DATA_W -1:WORD_W];
+    wire [    WORD_W -1:0] mem_addrb_lsb = mem_addrb[     WORD_W -1:     0];
     
-        .WRCLK      (clk_bus),
-        .WREN       (ena),
-        .WE         ({4{wea}}),
-        .WRADDR     (addra),
-        .DI         (dina),
-        
-        .RDCLK      (clk),
-        .RDEN       (enb),
-        .REGCE      (regceb),
-        .RDADDR     (addrb),
-        .DO         (doutb)
-    );
+    always @(posedge clk)
+        //
+        if (enb)
+            doutb_reg1 <= addrb[0] ? mem_addrb_msb : mem_addrb_lsb;
+            
+    always @(posedge clk)
+        //
+        if (regceb)
+            doutb_reg2 <= doutb_reg1;
     
     
 endmodule
diff --git a/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v b/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v
index c74daac..586cadf 100644
--- a/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v
+++ b/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v
@@ -33,41 +33,34 @@ module modexpng_sdp_36k_x32_x16_wrapper_generic
 
     
     //
-    // BRAM_SDP_MACRO
+    // Memory
     //
-    BRAM_SDP_MACRO #
-    (
-        .DEVICE                 ("7SERIES"),
-        
-        .BRAM_SIZE              ("36Kb"),
-        
-        .WRITE_WIDTH            (WORD_W),
-        .READ_WIDTH             (BUS_DATA_W),
-        
-        .DO_REG                 (0),
-        .WRITE_MODE             ("READ_FIRST"),
-        
-        .SRVAL                  (72'h000000000000000000),
-        .INIT                   (72'h000000000000000000),
-
-        .INIT_FILE              ("NONE"),
-        .SIM_COLLISION_CHECK    ("NONE")
-    )
-    BRAM_SDP_MACRO_inst
-    (
-        .RST        (1'b0),
+    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
+   
+    //
+    // Write Port
+    //
+    wire [BANK_ADDR_W + BUS_OP_ADDR_W -2:0] addra_msb = addra[BANK_ADDR_W + BUS_OP_ADDR_W -1:1];
+    wire                                    addra_lsb = addra[0];
+    
+    always @(posedge clk)
+        //
+        if (ena && wea) begin
+           if (addra_lsb) mem[addra_msb][BUS_DATA_W-1:WORD_W] <= dina;
+           else           mem[addra_msb][    WORD_W-1:     0] <= dina;
+        end
+            
+    //
+    // Read Port
+    //
+    reg [BUS_DATA_W -1:0] doutb_reg;
     
-        .WRCLK      (clk),
-        .WREN       (ena),
-        .WE         ({2{wea}}),
-        .WRADDR     (addra),
-        .DI         (dina),
+    assign doutb = doutb_reg;
         
-        .RDCLK      (clk_bus),
-        .RDEN       (enb),
-        .REGCE      (1'b0),
-        .RDADDR     (addrb),
-        .DO         (doutb)
-    );
+    always @(posedge clk_bus)
+        //
+        if (enb)
+            doutb_reg <= mem[addrb];
+            
     
 endmodule
diff --git a/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v b/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v
index 5e69bef..fda7cf6 100644
--- a/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v
+++ b/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v
@@ -34,6 +34,48 @@ module modexpng_tdp_36k_x16_x32_wrapper_generic
     output [              WORD_W        -1:0] doutb;
 
     
+    //
+    // Memory
+    //
+    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
+   
+    //
+    // Read-Write Port
+    //
+    reg [BUS_DATA_W -1:0] douta_reg;
+    
+    assign douta = douta_reg;
+    
+    always @(posedge clk_bus)
+        //
+        if (ena) begin
+            if (wea) mem[addra] <= dina;
+            douta_reg <= mem[addra];
+        end
+            
+    //
+    // Read Port
+    //
+    reg [WORD_W -1:0] doutb_reg1;
+    reg [WORD_W -1:0] doutb_reg2;
+    
+    assign doutb = doutb_reg2;
+    
+    wire [BUS_DATA_W -1:0] mem_addrb = mem[addrb[BANK_ADDR_W + OP_ADDR_W -1:1]];
+    
+    wire [    WORD_W -1:0] mem_addrb_msb = mem_addrb[ BUS_DATA_W -1:WORD_W];
+    wire [    WORD_W -1:0] mem_addrb_lsb = mem_addrb[     WORD_W -1:     0];
+    
+    always @(posedge clk)
+        //
+        if (enb)
+            doutb_reg1 <= addrb[0] ? mem_addrb_msb : mem_addrb_lsb;
+            
+    always @(posedge clk)
+        //
+        if (regceb)
+            doutb_reg2 <= doutb_reg1;
+/*    
     //
     // BRAM_TDP_MACRO
     //
@@ -84,5 +126,6 @@ module modexpng_tdp_36k_x16_x32_wrapper_generic
       .DIB      ({WORD_W{1'b0}}),
       .DOB      (doutb)
    );
+   */
     
 endmodule
diff --git a/rtl/modexpng_uop_rom.v b/rtl/modexpng_uop_rom.v
index 522e9ca..5d6308c 100644
--- a/rtl/modexpng_uop_rom.v
+++ b/rtl/modexpng_uop_rom.v
@@ -15,6 +15,8 @@ module modexpng_uop_rom
     always @(posedge clk)
         //
         case (addr)
+            //
+            // CRT mode
             //
             7'd000:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N,        BANK_WIDE_N, BANK_DNC         }; //
             7'd001:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N,        BANK_WIDE_N, BANK_DNC         }; //
@@ -107,9 +109,27 @@ module modexpng_uop_rom
             7'd058:  data <= {UOP_OPCODE_PROPAGATE_CARRIES,   UOP_CRT_DNC, UOP_NPQ_N,   UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC,      BANK_NARROW_A,      BANK_DNC,    BANK_NARROW_A    }; //
                                                                                                                                                                                          //
             7'd059:  data <= {UOP_OPCODE_OUTPUT_FROM_NARROW,  UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC,      BANK_NARROW_A,      BANK_DNC,    BANK_OUT_S       }; //
+            //
+            // Non-CRT Mode (i.e. only when "D" is known)
+            //
+            7'd064:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N,        BANK_WIDE_N, BANK_DNC         }; //
+            7'd065:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N,        BANK_WIDE_N, BANK_DNC         }; //
+            7'd066:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_X,        BANK_WIDE_A, BANK_DNC         }; //
+            7'd067:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_Y,        BANK_WIDE_A, BANK_DNC         }; //
+            7'd068:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_M,        BANK_WIDE_E, BANK_DNC         }; //
+            7'd069:  data <= {UOP_OPCODE_INPUT_TO_WIDE,       UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_M,        BANK_WIDE_E, BANK_DNC         }; //
+                                                                                                                                                                                         //
+            7'd070:  data <= {UOP_OPCODE_INPUT_TO_NARROW,     UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N_COEFF,  BANK_DNC,    BANK_NARROW_COEFF}; //
+            7'd071:  data <= {UOP_OPCODE_INPUT_TO_NARROW,     UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N_COEFF,  BANK_DNC,    BANK_NARROW_COEFF}; //
+            7'd072:  data <= {UOP_OPCODE_INPUT_TO_NARROW,     UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N_FACTOR, BANK_DNC,    BANK_NARROW_A    }; //
+            7'd073:  data <= {UOP_OPCODE_INPUT_TO_NARROW,     UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_N_FACTOR, BANK_DNC,    BANK_NARROW_A    }; //
+            7'd074:  data <= {UOP_OPCODE_INPUT_TO_NARROW,     UOP_CRT_X,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_M,        BANK_DNC,    BANK_NARROW_E    }; //
+            7'd075:  data <= {UOP_OPCODE_INPUT_TO_NARROW,     UOP_CRT_Y,   UOP_NPQ_N,   UOP_AUX_1,   UOP_LADDER_DNC, BANK_DNC,      BANK_IN_1_M,        BANK_DNC,    BANK_NARROW_E    }; //
                                                                                                                                                                                          //
             default: data <= {UOP_OPCODE_STOP,                UOP_CRT_DNC, UOP_NPQ_DNC, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC,      BANK_DNC,           BANK_DNC,    BANK_DNC         }; //
             //
+            
+            
         endcase
 
 endmodule
-- 
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