From 584393ac5fc9bbe80887702ec2fc97bee999c5e7 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 21 Oct 2019 15:13:01 +0300 Subject: Further work: - added core wrapper - fixed module resets across entire core (all the resets are now consistently active-low) - continued refactoring --- rtl/modexpng_uop_engine.v | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'rtl/modexpng_uop_engine.v') diff --git a/rtl/modexpng_uop_engine.v b/rtl/modexpng_uop_engine.v index 8ad2122..c7b064a 100644 --- a/rtl/modexpng_uop_engine.v +++ b/rtl/modexpng_uop_engine.v @@ -1,7 +1,7 @@ module modexpng_uop_engine ( clk, - rst, + rst_n, ena, rdy, @@ -83,7 +83,7 @@ module modexpng_uop_engine // Ports // input clk; - input rst; + input rst_n; input ena; output rdy; @@ -369,9 +369,9 @@ module modexpng_uop_engine // // UOP Trigger Logic // - always @(posedge clk) + always @(posedge clk or negedge rst_n) // - if (rst) begin + if (!rst_n) begin io_mgr_ena_r <= 1'b0; mmm_ena_x_r <= 1'b0; mmm_ena_y_r <= 1'b0; @@ -618,10 +618,10 @@ module modexpng_uop_engine // // UOP FSM Process // - always @(posedge clk) + always @(posedge clk or negedge rst_n) // - if (rst) uop_fsm_state <= UOP_FSM_STATE_IDLE; - else uop_fsm_state <= uop_fsm_state_next; + if (!rst_n) uop_fsm_state <= UOP_FSM_STATE_IDLE; + else uop_fsm_state <= uop_fsm_state_next; // @@ -645,9 +645,9 @@ module modexpng_uop_engine reg rdy_r = 1'b1; assign rdy = rdy_r; - always @(posedge clk) + always @(posedge clk or negedge rst_n) // - if (rst) rdy_r <= 1'b1; + if (!rst_n) rdy_r <= 1'b1; else case (uop_fsm_state) UOP_FSM_STATE_IDLE: rdy_r <= ~ena; UOP_FSM_STATE_DECODE: rdy_r <= uop_opcode_is_stop; -- cgit v1.2.3