From 584393ac5fc9bbe80887702ec2fc97bee999c5e7 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Mon, 21 Oct 2019 15:13:01 +0300
Subject: Further work:  - added core wrapper  - fixed module resets across
 entire core (all the resets are now consistently    active-low)  - continued
 refactoring

---
 rtl/modexpng_reductor.v | 29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

(limited to 'rtl/modexpng_reductor.v')

diff --git a/rtl/modexpng_reductor.v b/rtl/modexpng_reductor.v
index c9de32d..9a95f55 100644
--- a/rtl/modexpng_reductor.v
+++ b/rtl/modexpng_reductor.v
@@ -1,6 +1,6 @@
 module modexpng_reductor
 (
-    clk, rst,
+    clk, rst_n,
     ena, rdy,
     word_index_last,
     sel_wide_out, sel_narrow_out,
@@ -14,13 +14,10 @@ module modexpng_reductor
     // Headers
     //
     `include "modexpng_parameters.vh"
-    //`include "../rtl_1/modexpng_mmm_fsm.vh"
-    
-    //`include "../rtl_1/modexpng_parameters_x8.vh"
 
 
     input                        clk;
-    input                        rst;
+    input                        rst_n;
     input                        ena;
     output                       rdy;
     /*
@@ -70,11 +67,11 @@ module modexpng_reductor
 
     assign rdy = rdy_reg;
     
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) rdy_reg <= 1'b1;
+        if (!rst_n)                rdy_reg <= 1'b1;
         else begin
-            if (rdy && ena) rdy_reg <= 1'b0;
+            if (rdy && ena)        rdy_reg <= 1'b0;
             if (!rdy && !busy_now) rdy_reg <= 1'b1;
         end
         
@@ -103,9 +100,9 @@ module modexpng_reductor
     reg [17:0] rcmb_y_dout_dly2;
     reg [17:0] rcmb_y_dout_dly3;
     
-    always @(posedge clk) 
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) begin
+        if (!rst_n) begin
             rcmb_xy_valid_dly1 <= 1'b0;
             rcmb_xy_valid_dly2 <= 1'b0;
             rcmb_xy_valid_dly3 <= 1'b0;
@@ -283,9 +280,9 @@ module modexpng_reductor
     //
     //
     //
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) begin
+        if (!rst_n) begin
             clear_rdct_wide;
             clear_rdct_narrow;
         end else begin
@@ -325,17 +322,17 @@ module modexpng_reductor
 
     assign busy_now = busy_now_shreg[2];
     
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) busy_now_shreg <= {3{1'b0}};
+        if (!rst_n)         busy_now_shreg <= {3{1'b0}};
         else begin
             if (rdy && ena) busy_now_shreg <= {3{1'b1}};
             else            busy_now_shreg <= {busy_now_shreg[1:0], busy_next};
         end
     
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) busy_next <= 1'b0;
+        if (!rst_n) busy_next <= 1'b0;
         else begin
             if (rdy && ena) busy_next <= 1'b1;
             if (!rdy && rcmb_xy_valid_dly3 && (rcmb_xy_bank_dly3 == BANK_RCMB_EXT)) busy_next <= 1'b0;    
-- 
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