From c6029af4482192c3e25ef0f6561bfbefa76e75ec Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 21 Jan 2020 00:11:42 +0300 Subject: Refactored MMM recombinator module, accomodated the changes in DSP slice wrapper names. --- rtl/modexpng_recombinator_block.v | 1244 ++++++++++++++++++------------------- 1 file changed, 599 insertions(+), 645 deletions(-) (limited to 'rtl/modexpng_recombinator_block.v') diff --git a/rtl/modexpng_recombinator_block.v b/rtl/modexpng_recombinator_block.v index 077ae47..f6e23e5 100644 --- a/rtl/modexpng_recombinator_block.v +++ b/rtl/modexpng_recombinator_block.v @@ -53,58 +53,58 @@ module modexpng_recombinator_block `include "modexpng_mmm_dual_fsm.vh" - input clk; - input rst_n; - input ena; - output rdy; - input [MMM_FSM_STATE_W-1:0] fsm_state_next; - input [7:0] word_index_last; - input dsp_xy_ce_p; - input [9*47-1:0] dsp_x_p; - input [9*47-1:0] dsp_y_p; - input [ 4:0] col_index; - input [ 4:0] col_index_last; + input clk; + input rst_n; + input ena; + output rdy; + input [MMM_FSM_STATE_W -1:0] fsm_state_next; + input [ OP_ADDR_W -1:0] word_index_last; + input dsp_xy_ce_p; + input [ MAC_W * NUM_MULTS_AUX -1:0] dsp_x_p; + input [ MAC_W * NUM_MULTS_AUX -1:0] dsp_y_p; + input [ COL_INDEX_W -1:0] col_index; + input [ COL_INDEX_W -1:0] col_index_last; - input [ BANK_ADDR_W -1:0] rd_narrow_xy_bank; - input [ 7:0] rd_narrow_xy_addr; + input [ BANK_ADDR_W -1:0] rd_narrow_xy_bank; + input [ OP_ADDR_W -1:0] rd_narrow_xy_addr; - output [ BANK_ADDR_W -1:0] rcmb_wide_xy_bank; - output [ 7:0] rcmb_wide_xy_addr; - output [ 17:0] rcmb_wide_x_dout; - output [ 17:0] rcmb_wide_y_dout; - output rcmb_wide_xy_valid; + output [ BANK_ADDR_W -1:0] rcmb_wide_xy_bank; + output [ OP_ADDR_W -1:0] rcmb_wide_xy_addr; + output [ WORD_EXT_W -1:0] rcmb_wide_x_dout; + output [ WORD_EXT_W -1:0] rcmb_wide_y_dout; + output rcmb_wide_xy_valid; - output [ BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; - output [ 7:0] rcmb_narrow_xy_addr; - output [ 17:0] rcmb_narrow_x_dout; - output [ 17:0] rcmb_narrow_y_dout; - output rcmb_narrow_xy_valid; + output [ BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; + output [ OP_ADDR_W -1:0] rcmb_narrow_xy_addr; + output [ WORD_EXT_W -1:0] rcmb_narrow_x_dout; + output [ WORD_EXT_W -1:0] rcmb_narrow_y_dout; + output rcmb_narrow_xy_valid; - output [ BANK_ADDR_W -1:0] rdct_narrow_xy_bank; - output [ 7:0] rdct_narrow_xy_addr; - output [ 17:0] rdct_narrow_x_dout; - output [ 17:0] rdct_narrow_y_dout; - output rdct_narrow_xy_valid; + output [ BANK_ADDR_W -1:0] rdct_narrow_xy_bank; + output [ OP_ADDR_W -1:0] rdct_narrow_xy_addr; + output [ WORD_EXT_W -1:0] rdct_narrow_x_dout; + output [ WORD_EXT_W -1:0] rdct_narrow_y_dout; + output rdct_narrow_xy_valid; // // Latches // - reg [1*47-1:0] dsp_x_p_latch[0:8]; - reg [1*47-1:0] dsp_y_p_latch[0:8]; + reg [MAC_W-1:0] dsp_x_p_latch[0:NUM_MULTS_AUX-1]; + reg [MAC_W-1:0] dsp_y_p_latch[0:NUM_MULTS_AUX-1]; // // Mapping // - wire [46:0] dsp_x_p_split[0:8]; - wire [46:0] dsp_y_p_split[0:8]; + wire [MAC_W-1:0] dsp_x_p_split[0:NUM_MULTS_AUX-1]; + wire [MAC_W-1:0] dsp_y_p_split[0:NUM_MULTS_AUX-1]; genvar z; - generate for (z=0; z<(NUM_MULTS+1); z=z+1) + generate for (z=0; z