From 29fb6afd018c601a2e0c7376656d5e37beb565d6 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 1 Oct 2019 15:01:43 +0300 Subject: Started working on the pipelined Montgomery modular multiplier. Currently can do the "square" part of the multiplication, i.e. compute the twice larger intermediate product AB = A * B. --- rtl/modexpng_mmm_col_index.v | 90 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 rtl/modexpng_mmm_col_index.v (limited to 'rtl/modexpng_mmm_col_index.v') diff --git a/rtl/modexpng_mmm_col_index.v b/rtl/modexpng_mmm_col_index.v new file mode 100644 index 0000000..b904795 --- /dev/null +++ b/rtl/modexpng_mmm_col_index.v @@ -0,0 +1,90 @@ +module modexpng_mmm_col_index +( + clk, + index_last, + fsm_state_next, + col_index, + col_index_done, + col_index_zero, + col_index_next, + col_index_prev +); + + + // + // Includes + // + //`include "modexpng_parameters.vh" + //`include "modexpng_parameters_x8.vh" + `include "modexpng_mmm_fsm.vh" + + + // + // Parameters + // + parameter INDEX_WIDTH = 6; + + + // + // Ports + // + input clk; + input [ INDEX_WIDTH-1:0] index_last; + input [FSM_STATE_WIDTH-1:0] fsm_state_next; + output [ INDEX_WIDTH-4:0] col_index; + output col_index_done; + output [ INDEX_WIDTH-4:0] col_index_zero; + output [ INDEX_WIDTH-4:0] col_index_next; + output [ INDEX_WIDTH-4:0] col_index_prev; + + + // + // Registers + // + reg [INDEX_WIDTH-4:0] col_index_reg; + reg [INDEX_WIDTH-4:0] col_index_last; + reg [INDEX_WIDTH-4:0] col_index_dly; + + + // + // Mapping + // + assign col_index = col_index_reg; + assign col_index_prev = col_index_dly; + + + // + // Handy Wires + // + assign col_index_done = col_index == col_index_last; + assign col_index_zero = {(INDEX_WIDTH-3){1'b0}}; + assign col_index_next = col_index + 1'b1; + + + // + // Increment Logic + // + always @(posedge clk) + // + case (fsm_state_next) + // + FSM_STATE_MULT_SQUARE_COL_0_TRIG: begin + col_index_reg <= col_index_zero; + col_index_last <= index_last[INDEX_WIDTH-1:3]; + end + // + FSM_STATE_MULT_SQUARE_COL_N_TRIG: + col_index_reg <= col_index_next; + // + endcase + + + // + // Delay Logic + // + always @(posedge clk) + // + col_index_dly <= col_index; + + +endmodule -- cgit v1.2.3