From fde62e373fdfcefefb7da10757a3db933160c911 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 1 Oct 2019 15:16:58 +0300 Subject: Major rewrite (different core hierarchy, buses, wrappers, etc). --- rtl/modexpng_mac.v | 54 ------------------------------------------------------ 1 file changed, 54 deletions(-) delete mode 100644 rtl/modexpng_mac.v (limited to 'rtl/modexpng_mac.v') diff --git a/rtl/modexpng_mac.v b/rtl/modexpng_mac.v deleted file mode 100644 index 9105dab..0000000 --- a/rtl/modexpng_mac.v +++ /dev/null @@ -1,54 +0,0 @@ -module modexpng_mac -( - clk, - ce, clr, - casc_a, - a_in, b_in, p_out, - a_casc_in, a_casc_out -); - - input clk; - input ce; - input clr; - input casc_a; - input [16:0] a_in; - input [16:0] b_in; - output [46:0] p_out; - input [16:0] a_casc_in; - output [16:0] a_casc_out; - - reg [16:0] a_reg; - reg [16:0] b_reg; - assign a_casc_out = a_reg; - always @(posedge clk) - // - if (ce) {b_reg, a_reg} <= {b_in, casc_a ? a_casc_in : a_in}; - - reg ce_dly1; - reg ce_dly2; - always @(posedge clk) - // - {ce_dly2, ce_dly1} <= {ce_dly1, ce}; - - reg clr_dly1; - reg clr_dly2; - always @(posedge clk) begin - // - if (ce) clr_dly1 <= clr; - if (ce_dly1) clr_dly2 <= clr_dly1; - // - end - - reg [33:0] m_reg; - wire [46:0] m_reg_ext = {{13{1'b0}}, m_reg}; - always @(posedge clk) - // - if (ce_dly1) m_reg <= {{17{1'b0}}, a_reg} * {{17{1'b0}}, b_reg}; - - reg [46:0] p_reg; - assign p_out = p_reg; - always @(posedge clk) - // - if (ce_dly2) p_reg <= clr_dly2 ? m_reg_ext : p_reg + m_reg_ext; - -endmodule -- cgit v1.2.3