From 02247784f18dc683d5873a52c1650e72f02273b5 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Thu, 3 Oct 2019 16:50:25 +0300 Subject: Added more micro-operations, entire Montgomery exponentiation ladder works now. --- bench/tb_mmm_x8_dual.v | 327 ------------------------------------------------- 1 file changed, 327 deletions(-) delete mode 100644 bench/tb_mmm_x8_dual.v (limited to 'bench/tb_mmm_x8_dual.v') diff --git a/bench/tb_mmm_x8_dual.v b/bench/tb_mmm_x8_dual.v deleted file mode 100644 index aa25900..0000000 --- a/bench/tb_mmm_x8_dual.v +++ /dev/null @@ -1,327 +0,0 @@ -`timescale 1ns / 1ps - -module tb_mmm_x8_dual; - - - // - // Headers - // - `include "../rtl/modexpng_parameters.vh" - `include "../rtl/modexpng_parameters_x8.vh" - - - // - // Settings - // - localparam INDEX_WIDTH = 6; - - wire [INDEX_WIDTH-1:0] index_last = 31; // 512 bits - - - // - // Clock - // - `define CLK_FREQUENCY_MHZ 100.0 - `define CLK_PERIOD_NS (1000.0 / `CLK_FREQUENCY_MHZ) - `define CLK_PERIOD_HALF_NS (0.5 * `CLK_PERIOD_NS) - - reg clk = 1'b0; - - always begin - #`CLK_PERIOD_HALF_NS clk = 1'b1; - #`CLK_PERIOD_HALF_NS clk = 1'b0; - end - - - // - // Reset - // - reg rst = 1'b1; - wire rst_n = ~rst; - - - // - // Control - // - reg ena = 1'b0; - wire rdy; - - reg mode; - reg transfer; - - - // - // Interface - // - - - // - // Interface - Data Buses - // - wire [NUM_MULTS*WORD_WIDTH-1:0] x_din; - wire [NUM_MULTS*WORD_WIDTH-1:0] y_din; - wire [NUM_MULTS*WORD_WIDTH-1:0] x_dout; - wire [NUM_MULTS*WORD_WIDTH-1:0] y_dout; - - - // - // Interface - Address Buses - // - wire [INDEX_WIDTH-4:0] x_din_addr; - wire [INDEX_WIDTH-4:0] y_din_addr; - wire [INDEX_WIDTH-4:0] x_dout_addr; - wire [INDEX_WIDTH-4:0] y_dout_addr; - - - // - // Interface - Enable Buses - // - wire [ 1-1:0] x_din_ena; - wire [ 1-1:0] y_din_ena; - wire [ 1-1:0] x_din_reg_ena; - wire [ 1-1:0] y_din_reg_ena; - wire [NUM_MULTS-1:0] x_dout_ena; - wire [NUM_MULTS-1:0] y_dout_ena; - - - // - // Interface - Bank Buses - // - wire [3-1:0] x_din_bank; - wire [3-1:0] y_din_bank; - wire [3-1:0] x_dout_bank; - wire [3-1:0] y_dout_bank; - - - // - // Operands - // - reg [WORD_WIDTH-1:0] T1[0:2**INDEX_WIDTH-1]; - reg [WORD_WIDTH-1:0] T2[0:2**INDEX_WIDTH-1]; - reg [WORD_WIDTH-1:0] N[0:2**INDEX_WIDTH-1]; - reg [WORD_WIDTH-1:0] N_COEFF[0:2**INDEX_WIDTH]; - - - // - // Memories - // - genvar z; - generate for (z=0; z 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295