From 584393ac5fc9bbe80887702ec2fc97bee999c5e7 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 21 Oct 2019 15:13:01 +0300 Subject: Further work: - added core wrapper - fixed module resets across entire core (all the resets are now consistently active-low) - continued refactoring --- bench/tb_core_full_512.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'bench/tb_core_full_512.v') diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v index e2604f0..cbcdd1d 100644 --- a/bench/tb_core_full_512.v +++ b/bench/tb_core_full_512.v @@ -238,7 +238,7 @@ module tb_core_full_512; sync_clk_bus; // switch to slow bus clock core_set_input; // write to core input banks - /* + sync_clk; // switch to fast core clock core_set_crt_mode(1); // enable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -247,7 +247,7 @@ module tb_core_full_512; sync_clk_bus; // switch to slow bus clock core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values - */ + sync_clk; // switch to fast core clock core_set_crt_mode(0); // disable CRT signing core_pulse_next; // assert 'next' bit for one cycle -- cgit v1.2.3