From b0cbd33df04f024a7dea928756f4937b79c91631 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 21 Jan 2020 00:13:33 +0300 Subject: Refactored the MMM module, now uses meaningful constant names from the include file, not hardcoded widths. --- rtl/modexpng_mmm_dual.v | 733 +++++++++++++++++++++++++----------------------- 1 file changed, 380 insertions(+), 353 deletions(-) diff --git a/rtl/modexpng_mmm_dual.v b/rtl/modexpng_mmm_dual.v index 8d8b83d..bb1a55c 100644 --- a/rtl/modexpng_mmm_dual.v +++ b/rtl/modexpng_mmm_dual.v @@ -94,72 +94,73 @@ module modexpng_mmm_dual // // Ports // - input clk; - input rst_n; + input clk; + input rst_n; - input ena; - output rdy; + input ena; + output rdy; - input ladder_mode; - input [7:0] word_index_last; - input [7:0] word_index_last_minus1; - input force_unity_b; - input only_reduce; - input just_multiply; + input ladder_mode; + input [ OP_ADDR_W -1:0] word_index_last; + input [ OP_ADDR_W -1:0] word_index_last_minus1; + input force_unity_b; + input only_reduce; + input just_multiply; - input [BANK_ADDR_W-1:0] sel_wide_in; - input [BANK_ADDR_W-1:0] sel_narrow_in; + input [BANK_ADDR_W -1:0] sel_wide_in; + input [BANK_ADDR_W -1:0] sel_narrow_in; - output rd_wide_xy_ena; - output rd_wide_xy_ena_aux; - output [ BANK_ADDR_W -1:0] rd_wide_xy_bank; - output [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; - output [ 8*NUM_MULTS/2-1:0] rd_wide_xy_addr; - output [ 8-1:0] rd_wide_xy_addr_aux; - input [18*NUM_MULTS/2-1:0] rd_wide_x_din; - input [18*NUM_MULTS/2-1:0] rd_wide_y_din; - input [ 18-1:0] rd_wide_x_din_aux; - input [ 18-1:0] rd_wide_y_din_aux; + output rd_wide_xy_ena; + output rd_wide_xy_ena_aux; + output [BANK_ADDR_W -1:0] rd_wide_xy_bank; + output [BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; + + output [ OP_ADDR_W * NUM_MULTS_HALF -1:0] rd_wide_xy_addr; + output [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux; + input [ WORD_EXT_W * NUM_MULTS_HALF -1:0] rd_wide_x_din; + input [ WORD_EXT_W * NUM_MULTS_HALF -1:0] rd_wide_y_din; + input [ WORD_EXT_W -1:0] rd_wide_x_din_aux; + input [ WORD_EXT_W -1:0] rd_wide_y_din_aux; - output rd_narrow_xy_ena; - output [ BANK_ADDR_W -1:0] rd_narrow_xy_bank; - output [ 7:0] rd_narrow_xy_addr; - input [18-1:0] rd_narrow_x_din; - input [18-1:0] rd_narrow_y_din; + output rd_narrow_xy_ena; + output [BANK_ADDR_W -1:0] rd_narrow_xy_bank; + output [ OP_ADDR_W -1:0] rd_narrow_xy_addr; + input [ WORD_EXT_W -1:0] rd_narrow_x_din; + input [ WORD_EXT_W -1:0] rd_narrow_y_din; - output [BANK_ADDR_W -1:0] rcmb_wide_xy_bank; - output [ 7:0] rcmb_wide_xy_addr; - output [17:0] rcmb_wide_x_dout; - output [17:0] rcmb_wide_y_dout; - output rcmb_wide_xy_valid; + output [BANK_ADDR_W -1:0] rcmb_wide_xy_bank; + output [ OP_ADDR_W -1:0] rcmb_wide_xy_addr; + output [ WORD_EXT_W -1:0] rcmb_wide_x_dout; + output [ WORD_EXT_W -1:0] rcmb_wide_y_dout; + output rcmb_wide_xy_valid; - output [BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; - output [ 7:0] rcmb_narrow_xy_addr; - output [17:0] rcmb_narrow_x_dout; - output [17:0] rcmb_narrow_y_dout; - output rcmb_narrow_xy_valid; + output [BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; + output [ OP_ADDR_W -1:0] rcmb_narrow_xy_addr; + output [ WORD_EXT_W -1:0] rcmb_narrow_x_dout; + output [ WORD_EXT_W -1:0] rcmb_narrow_y_dout; + output rcmb_narrow_xy_valid; - output [BANK_ADDR_W -1:0] rcmb_xy_bank; - output [ 7:0] rcmb_xy_addr; - output [17:0] rcmb_x_dout; - output [17:0] rcmb_y_dout; - output rcmb_xy_valid; + output [BANK_ADDR_W -1:0] rcmb_xy_bank; + output [ OP_ADDR_W -1:0] rcmb_xy_addr; + output [ WORD_EXT_W -1:0] rcmb_x_dout; + output [ WORD_EXT_W -1:0] rcmb_y_dout; + output rcmb_xy_valid; - output rdct_ena; - input rdct_rdy; + output rdct_ena; + input rdct_rdy; // // FSM Declaration // - reg [MMM_FSM_STATE_W-1:0] fsm_state = MMM_FSM_STATE_IDLE; - reg [MMM_FSM_STATE_W-1:0] fsm_state_next; + reg [MMM_FSM_STATE_W -1:0] fsm_state = MMM_FSM_STATE_IDLE; + reg [MMM_FSM_STATE_W -1:0] fsm_state_next; - wire [MMM_FSM_STATE_W-1:0] fsm_state_after_idle; - wire [MMM_FSM_STATE_W-1:0] fsm_state_after_mult_square; - wire [MMM_FSM_STATE_W-1:0] fsm_state_after_mult_triangle; - wire [MMM_FSM_STATE_W-1:0] fsm_state_after_mult_rectangle; - wire [MMM_FSM_STATE_W-1:0] fsm_state_after_square_holdoff; + wire [MMM_FSM_STATE_W -1:0] fsm_state_after_idle; + wire [MMM_FSM_STATE_W -1:0] fsm_state_after_mult_square; + wire [MMM_FSM_STATE_W -1:0] fsm_state_after_mult_triangle; + wire [MMM_FSM_STATE_W -1:0] fsm_state_after_mult_rectangle; + wire [MMM_FSM_STATE_W -1:0] fsm_state_after_square_holdoff; // @@ -174,48 +175,55 @@ module modexpng_mmm_dual // // Storage Control Interface // - reg wide_xy_ena = 1'b0; - reg wide_xy_ena_aux = 1'b0; - reg [ BANK_ADDR_W -1:0] wide_xy_bank; - reg [ BANK_ADDR_W -1:0] wide_xy_bank_aux; - reg [ 8-1:0] wide_xy_addr[0:3]; - reg [ 8-1:0] wide_xy_addr_aux; + reg wide_xy_ena = 1'b0; + reg wide_xy_ena_aux = 1'b0; + reg [BANK_ADDR_W -1:0] wide_xy_bank; + reg [BANK_ADDR_W -1:0] wide_xy_bank_aux; + reg [ OP_ADDR_W -1:0] wide_xy_addr[0:NUM_MULTS_HALF-1]; + reg [ OP_ADDR_W -1:0] wide_xy_addr_aux; + + reg narrow_xy_ena = 1'b0; + reg [BANK_ADDR_W -1:0] narrow_xy_bank; + reg [ OP_ADDR_W -1:0] narrow_xy_addr; + reg [ OP_ADDR_W -1:0] narrow_xy_addr_dly; + wire [ OP_ADDR_W -1:0] narrow_xy_addr_inc = narrow_xy_addr + 1'b1; - reg narrow_xy_ena = 1'b0; - reg [ BANK_ADDR_W -1:0] narrow_xy_bank; - reg [ 7:0] narrow_xy_addr; - reg [ 7:0] narrow_xy_addr_dly; - assign rd_wide_xy_ena = wide_xy_ena; + // + // Outmap Port Mapping + // + assign rd_wide_xy_ena = wide_xy_ena; assign rd_wide_xy_ena_aux = wide_xy_ena_aux; - assign rd_wide_xy_bank = wide_xy_bank; + assign rd_wide_xy_bank = wide_xy_bank; assign rd_wide_xy_bank_aux = wide_xy_bank_aux; assign rd_wide_xy_addr_aux = wide_xy_addr_aux; - assign rd_narrow_xy_ena = narrow_xy_ena; - assign rd_narrow_xy_bank = narrow_xy_bank; - assign rd_narrow_xy_addr = narrow_xy_addr; + assign rd_narrow_xy_ena = narrow_xy_ena; + assign rd_narrow_xy_bank = narrow_xy_bank; + assign rd_narrow_xy_addr = narrow_xy_addr; genvar z; - generate for (z=0; z<(NUM_MULTS/2); z=z+1) + generate for (z=0; z 8'd0) - wide_xy_addr_next = wide_xy_addr_current - 1'b1; - else - wide_xy_addr_next = wide_xy_addr_last; - end + function [OP_ADDR_W-1:0] wide_xy_addr_next; + input [OP_ADDR_W-1:0] wide_xy_addr_current; + input [OP_ADDR_W-1:0] wide_xy_addr_last; + if (wide_xy_addr_current > OP_ADDR_ZERO) wide_xy_addr_next = wide_xy_addr_current - 1'b1; + else wide_xy_addr_next = wide_xy_addr_last; endfunction integer j; @@ -459,128 +460,143 @@ module modexpng_mmm_dual // // Wide Address // - for (j=0; j<(NUM_MULTS/2); j=j+1) + for (j=0; j