From 863cac90f320d6b7587177bc2df798c611fe510b Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 18 Nov 2019 15:12:34 +0300 Subject: Refactored reductor module. --- rtl/modexpng_reductor.v | 369 +++++++++++++++++++++++------------------------- 1 file changed, 178 insertions(+), 191 deletions(-) diff --git a/rtl/modexpng_reductor.v b/rtl/modexpng_reductor.v index a7c4983..dd9cfd9 100644 --- a/rtl/modexpng_reductor.v +++ b/rtl/modexpng_reductor.v @@ -36,8 +36,8 @@ module modexpng_reductor ena, rdy, word_index_last, sel_wide_out, sel_narrow_out, - /*rd_wide_xy_addr_aux, rd_wide_xy_bank_aux,*/ rd_wide_x_din_aux, rd_wide_y_din_aux, - rcmb_final_xy_bank, rcmb_final_xy_addr, rcmb_final_x_din, rcmb_final_y_din, rcmb_final_xy_valid, + rd_wide_x_din_aux, rd_wide_y_din_aux, + rcmb_final_xy_bank, rcmb_final_xy_addr, rcmb_final_x_din, rcmb_final_y_din, rcmb_final_xy_valid, rdct_wide_xy_bank, rdct_wide_xy_addr, rdct_wide_x_dout, rdct_wide_y_dout, rdct_wide_xy_valid, rdct_narrow_xy_bank, rdct_narrow_xy_addr, rdct_narrow_x_dout, rdct_narrow_y_dout, rdct_narrow_xy_valid ); @@ -48,89 +48,153 @@ module modexpng_reductor `include "modexpng_parameters.vh" - input clk; - input rst_n; - input ena; - output rdy; - /* - input [FSM_STATE_WIDTH-1:0] fsm_state_next;*/ - input [7:0] word_index_last;/* - input dsp_xy_ce_p; - */ - input [2:0] sel_wide_out; - input [2:0] sel_narrow_out; - /* - input [9*47-1:0] dsp_x_p; - input [9*47-1:0] dsp_y_p; - input [ 4:0] col_index; - input [ 4:0] col_index_last; - *//* - input [ 7:0] rd_narrow_xy_addr; - input [ 1:0] rd_narrow_xy_bank; - */ - //input [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; - //input [ 7:0] rd_wide_xy_addr_aux; - input [ 17:0] rd_wide_x_din_aux; - input [ 17:0] rd_wide_y_din_aux; // - input [ BANK_ADDR_W -1:0] rcmb_final_xy_bank; - input [ 7:0] rcmb_final_xy_addr; - input [ 17:0] rcmb_final_x_din; - input [ 17:0] rcmb_final_y_din; - input rcmb_final_xy_valid; - - output [ 2:0] rdct_wide_xy_bank; - output [ 7:0] rdct_wide_xy_addr; - output [ 17:0] rdct_wide_x_dout; - output [ 17:0] rdct_wide_y_dout; - output rdct_wide_xy_valid; - - output [ 2:0] rdct_narrow_xy_bank; - output [ 7:0] rdct_narrow_xy_addr; - output [ 17:0] rdct_narrow_x_dout; - output [ 17:0] rdct_narrow_y_dout; - output rdct_narrow_xy_valid; + // Ports + // + input clk; + input rst_n; + input ena; + output rdy; + + input [ OP_ADDR_W -1:0] word_index_last; + + input [BANK_ADDR_W -1:0] sel_wide_out; + input [BANK_ADDR_W -1:0] sel_narrow_out; + + input [ WORD_EXT_W -1:0] rd_wide_x_din_aux; + input [ WORD_EXT_W -1:0] rd_wide_y_din_aux; + // + input [BANK_ADDR_W -1:0] rcmb_final_xy_bank; + input [ OP_ADDR_W -1:0] rcmb_final_xy_addr; + input [ WORD_EXT_W -1:0] rcmb_final_x_din; + input [ WORD_EXT_W -1:0] rcmb_final_y_din; + input rcmb_final_xy_valid; + output [BANK_ADDR_W -1:0] rdct_wide_xy_bank; + output [ OP_ADDR_W -1:0] rdct_wide_xy_addr; + output [ WORD_EXT_W -1:0] rdct_wide_x_dout; + output [ WORD_EXT_W -1:0] rdct_wide_y_dout; + output rdct_wide_xy_valid; + + output [BANK_ADDR_W -1:0] rdct_narrow_xy_bank; + output [ OP_ADDR_W -1:0] rdct_narrow_xy_addr; + output [ WORD_EXT_W -1:0] rdct_narrow_x_dout; + output [ WORD_EXT_W -1:0] rdct_narrow_y_dout; + output rdct_narrow_xy_valid; + + // - // Ready + // Output Registers // - reg rdy_reg = 1'b1; - wire busy_now; + reg [BANK_ADDR_W -1:0] wide_xy_bank; + reg [ OP_ADDR_W -1:0] wide_xy_addr; + reg [ WORD_EXT_W -1:0] wide_x_dout; + reg [ WORD_EXT_W -1:0] wide_y_dout; + reg wide_xy_valid = 1'b0; - assign rdy = rdy_reg; + reg [BANK_ADDR_W -1:0] narrow_xy_bank; + reg [ OP_ADDR_W -1:0] narrow_xy_addr; + reg [ WORD_EXT_W -1:0] narrow_x_dout; + reg [ WORD_EXT_W -1:0] narrow_y_dout; + reg narrow_xy_valid = 1'b0; + + + // + // Mapping + // + assign rdct_wide_xy_bank = wide_xy_bank; + assign rdct_wide_xy_addr = wide_xy_addr; + assign rdct_wide_x_dout = wide_x_dout; + assign rdct_wide_y_dout = wide_y_dout; + assign rdct_wide_xy_valid = wide_xy_valid; + + assign rdct_narrow_xy_bank = narrow_xy_bank; + assign rdct_narrow_xy_addr = narrow_xy_addr; + assign rdct_narrow_x_dout = narrow_x_dout; + assign rdct_narrow_y_dout = narrow_y_dout; + assign rdct_narrow_xy_valid = narrow_xy_valid; + + + // + // Helper Tasks + // + task _update_rdct_wide; + input [BANK_ADDR_W -1:0] bank; + input [ OP_ADDR_W -1:0] addr; + input [ WORD_EXT_W -1:0] dout_x; + input [ WORD_EXT_W -1:0] dout_y; + input valid; + begin + wide_xy_bank <= bank; + wide_xy_addr <= addr; + wide_x_dout <= dout_x; + wide_y_dout <= dout_y; + wide_xy_valid <= valid; + end + endtask - always @(posedge clk or negedge rst_n) - // - if (!rst_n) rdy_reg <= 1'b1; - else begin - if (rdy && ena) rdy_reg <= 1'b0; - if (!rdy && !busy_now) rdy_reg <= 1'b1; + task _update_rdct_narrow; + input [BANK_ADDR_W -1:0] bank; + input [ OP_ADDR_W -1:0] addr; + input [ WORD_EXT_W -1:0] dout_x; + input [ WORD_EXT_W -1:0] dout_y; + input valid; + begin + narrow_xy_bank <= bank; + narrow_xy_addr <= addr; + narrow_x_dout <= dout_x; + narrow_y_dout <= dout_y; + narrow_xy_valid <= valid; end - - + endtask + + task set_rdct_wide; + input [BANK_ADDR_W -1:0] bank; + input [ OP_ADDR_W -1:0] addr; + input [ WORD_EXT_W -1:0] dout_x; + input [ WORD_EXT_W -1:0] dout_y; + _update_rdct_wide(bank, addr, dout_x, dout_y, 1'b1); + endtask + + task set_rdct_narrow; + input [BANK_ADDR_W -1:0] bank; + input [ OP_ADDR_W -1:0] addr; + input [ WORD_EXT_W -1:0] dout_x; + input [ WORD_EXT_W -1:0] dout_y; + _update_rdct_narrow(bank, addr, dout_x, dout_y, 1'b1); + endtask + + task clear_rdct_wide; + _update_rdct_wide(BANK_DNC, OP_ADDR_DNC, WORD_EXT_DNC, WORD_EXT_DNC, 1'b0); + endtask + + task clear_rdct_narrow; + _update_rdct_narrow(BANK_DNC, OP_ADDR_DNC, WORD_EXT_DNC, WORD_EXT_DNC, 1'b0); + endtask + // // Pipeline (Delay Match) // - reg rcmb_xy_valid_dly1 = 1'b0; - reg rcmb_xy_valid_dly2 = 1'b0; - reg rcmb_xy_valid_dly3 = 1'b0; + reg rcmb_xy_valid_dly1 = 1'b0; + reg rcmb_xy_valid_dly2 = 1'b0; + reg rcmb_xy_valid_dly3 = 1'b0; reg [BANK_ADDR_W -1:0] rcmb_xy_bank_dly1; reg [BANK_ADDR_W -1:0] rcmb_xy_bank_dly2; reg [BANK_ADDR_W -1:0] rcmb_xy_bank_dly3; - reg [7:0] rcmb_xy_addr_dly1; - reg [7:0] rcmb_xy_addr_dly2; - reg [7:0] rcmb_xy_addr_dly3; + reg [ OP_ADDR_W -1:0] rcmb_xy_addr_dly1; + reg [ OP_ADDR_W -1:0] rcmb_xy_addr_dly2; + reg [ OP_ADDR_W -1:0] rcmb_xy_addr_dly3; - reg [17:0] rcmb_x_dout_dly1; - reg [17:0] rcmb_x_dout_dly2; - reg [17:0] rcmb_x_dout_dly3; + reg [ WORD_EXT_W -1:0] rcmb_x_dout_dly1; + reg [ WORD_EXT_W -1:0] rcmb_x_dout_dly2; + reg [ WORD_EXT_W -1:0] rcmb_x_dout_dly3; - reg [17:0] rcmb_y_dout_dly1; - reg [17:0] rcmb_y_dout_dly2; - reg [17:0] rcmb_y_dout_dly3; + reg [ WORD_EXT_W -1:0] rcmb_y_dout_dly1; + reg [ WORD_EXT_W -1:0] rcmb_y_dout_dly2; + reg [ WORD_EXT_W -1:0] rcmb_y_dout_dly3; always @(posedge clk or negedge rst_n) // @@ -144,7 +208,6 @@ module modexpng_reductor rcmb_xy_valid_dly3 <= rcmb_xy_valid_dly2; end - always @(posedge clk) begin // if (rcmb_final_xy_valid) begin @@ -169,19 +232,19 @@ module modexpng_reductor end // end - - - reg [ 1:0] rcmb_x_lsb_carry; - reg [15:0] rcmb_x_lsb_dummy; - reg [17:0] rcmb_x_lsb_dout; - - reg [ 1:0] rcmb_y_lsb_carry; - reg [15:0] rcmb_y_lsb_dummy; - reg [17:0] rcmb_y_lsb_dout; + + + // + // + // + reg [ CARRY_W -1:0] rcmb_x_lsb_carry; + reg [ WORD_W -1:0] rcmb_x_lsb_dummy; + reg [WORD_EXT_W -1:0] rcmb_x_lsb_dout; - //reg [17:0] reductor_fat_bram_x_msb_dout; - //reg reductor_fat_bram_x_msb_dout_valid = 1'b0; - //reg [ 7:0] reductor_fat_bram_x_msb_addr; + reg [ CARRY_W -1:0] rcmb_y_lsb_carry; + reg [ WORD_W -1:0] rcmb_y_lsb_dummy; + reg [WORD_EXT_W -1:0] rcmb_y_lsb_dout; + // // Carry Computation @@ -189,8 +252,8 @@ module modexpng_reductor always @(posedge clk) // if (ena) begin - rcmb_x_lsb_carry <= 2'b00; - rcmb_y_lsb_carry <= 2'b00; + rcmb_x_lsb_carry <= CARRY_ZERO; + rcmb_y_lsb_carry <= CARRY_ZERO; end else if (rcmb_xy_valid_dly3) // case (rcmb_xy_bank_dly3) @@ -201,112 +264,22 @@ module modexpng_reductor end BANK_RCMB_MH: - if (rcmb_xy_addr_dly3 == 8'd0) begin + if (rcmb_xy_addr_dly3 == OP_ADDR_ZERO) begin {rcmb_x_lsb_carry, rcmb_x_lsb_dummy} <= rcmb_x_dout_dly3 + rd_wide_x_din_aux + rcmb_x_lsb_carry; {rcmb_y_lsb_carry, rcmb_y_lsb_dummy} <= rcmb_y_dout_dly3 + rd_wide_y_din_aux + rcmb_y_lsb_carry; end endcase - - // - // Reduction - // - reg [ 2:0] wide_xy_bank; - reg [ 7:0] wide_xy_addr; - reg [ 17:0] wide_x_dout; - reg [ 17:0] wide_y_dout; - reg wide_xy_valid = 1'b0; - - reg [ 2:0] narrow_xy_bank; - reg [ 7:0] narrow_xy_addr; - reg [ 17:0] narrow_x_dout; - reg [ 17:0] narrow_y_dout; - reg narrow_xy_valid = 1'b0; - - assign rdct_wide_xy_bank = wide_xy_bank; - assign rdct_wide_xy_addr = wide_xy_addr; - assign rdct_wide_x_dout = wide_x_dout; - assign rdct_wide_y_dout = wide_y_dout; - assign rdct_wide_xy_valid = wide_xy_valid; - - assign rdct_narrow_xy_bank = narrow_xy_bank; - assign rdct_narrow_xy_addr = narrow_xy_addr; - assign rdct_narrow_x_dout = narrow_x_dout; - assign rdct_narrow_y_dout = narrow_y_dout; - assign rdct_narrow_xy_valid = narrow_xy_valid; - - task _update_rdct_wide; - input [ 2:0] bank; - input [ 7:0] addr; - input [17:0] dout_x; - input [17:0] dout_y; - input valid; - begin - wide_xy_bank <= bank; - wide_xy_addr <= addr; - wide_x_dout <= dout_x; - wide_y_dout <= dout_y; - wide_xy_valid <= valid; - end - endtask - - task _update_rdct_narrow; - input [ 2:0] bank; - input [ 7:0] addr; - input [17:0] dout_x; - input [17:0] dout_y; - input valid; - begin - narrow_xy_bank <= bank; - narrow_xy_addr <= addr; - narrow_x_dout <= dout_x; - narrow_y_dout <= dout_y; - narrow_xy_valid <= valid; - end - endtask - - task set_rdct_wide; - input [ 2:0] bank; - input [ 7:0] addr; - input [17:0] dout_x; - input [17:0] dout_y; - begin - _update_rdct_wide(bank, addr, dout_x, dout_y, 1'b1); - end - endtask - - task set_rdct_narrow; - input [ 2:0] bank; - input [ 7:0] addr; - input [17:0] dout_x; - input [17:0] dout_y; - begin - _update_rdct_narrow(bank, addr, dout_x, dout_y, 1'b1); - end - endtask - - task clear_rdct_wide; - begin - _update_rdct_wide(3'bXXX, 8'hXX, {18{1'bX}}, {18{1'bX}}, 1'b0); - end - endtask - - task clear_rdct_narrow; - begin - _update_rdct_narrow(3'bXXX, 8'hXX, {18{1'bX}}, {18{1'bX}}, 1'b0); - end - endtask - // // // - wire [17:0] sum_rdct_x = rcmb_x_dout_dly3 + rd_wide_x_din_aux; - wire [17:0] sum_rdct_y = rcmb_y_dout_dly3 + rd_wide_y_din_aux; + wire [WORD_EXT_W -1:0] sum_rdct_x = rcmb_x_dout_dly3 + rd_wide_x_din_aux; + wire [WORD_EXT_W -1:0] sum_rdct_y = rcmb_y_dout_dly3 + rd_wide_y_din_aux; - wire [17:0] sum_rdct_x_carry = sum_rdct_x + {16'h0000, rcmb_x_lsb_carry}; - wire [17:0] sum_rdct_y_carry = sum_rdct_y + {16'h0000, rcmb_y_lsb_carry}; + wire [WORD_EXT_W -1:0] sum_rdct_x_carry = sum_rdct_x + {WORD_ZERO, rcmb_x_lsb_carry}; + wire [WORD_EXT_W -1:0] sum_rdct_y_carry = sum_rdct_y + {WORD_ZERO, rcmb_y_lsb_carry}; // @@ -327,10 +300,10 @@ module modexpng_reductor case (rcmb_xy_bank_dly3) BANK_RCMB_MH: - if (rcmb_xy_addr_dly3 == 8'd1) begin - set_rdct_wide (sel_wide_out, 8'd0, sum_rdct_x_carry, sum_rdct_y_carry); - set_rdct_narrow(sel_narrow_out, 8'd0, sum_rdct_x_carry, sum_rdct_y_carry); - end else if (rcmb_xy_addr_dly3 > 8'd1) begin + if (rcmb_xy_addr_dly3 == OP_ADDR_ONE) begin + set_rdct_wide (sel_wide_out, OP_ADDR_ZERO, sum_rdct_x_carry, sum_rdct_y_carry); + set_rdct_narrow(sel_narrow_out, OP_ADDR_ZERO, sum_rdct_x_carry, sum_rdct_y_carry); + end else if (rcmb_xy_addr_dly3 > OP_ADDR_ONE) begin set_rdct_wide (sel_wide_out, rcmb_xy_addr_dly3 - 1'b1, sum_rdct_x, sum_rdct_y); set_rdct_narrow(sel_narrow_out, rcmb_xy_addr_dly3 - 1'b1, sum_rdct_x, sum_rdct_y); end @@ -345,30 +318,44 @@ module modexpng_reductor end - // - // Busy + // Internal Busy Flag Logic // - reg busy_next = 1'b0; - reg [2:0] busy_now_shreg = {3{1'b0}}; - - assign busy_now = busy_now_shreg[2]; + reg busy_next = 1'b0; + reg [2:0] busy_now_shreg = 3'b000; + wire busy_now = busy_now_shreg[2]; always @(posedge clk or negedge rst_n) // - if (!rst_n) busy_now_shreg <= {3{1'b0}}; + if (!rst_n) busy_now_shreg <= 3'b000; else begin - if (rdy && ena) busy_now_shreg <= {3{1'b1}}; + if (rdy && ena) busy_now_shreg <= 3'b111; else busy_now_shreg <= {busy_now_shreg[1:0], busy_next}; end always @(posedge clk or negedge rst_n) // - if (!rst_n) busy_next <= 1'b0; + if (!rst_n) busy_next <= 1'b0; else begin - if (rdy && ena) busy_next <= 1'b1; + if (rdy && ena) busy_next <= 1'b1; if (!rdy && rcmb_xy_valid_dly3 && (rcmb_xy_bank_dly3 == BANK_RCMB_EXT)) busy_next <= 1'b0; end + + // + // Ready Flag Logic + // + reg rdy_reg = 1'b1; + + assign rdy = rdy_reg; + always @(posedge clk or negedge rst_n) + // + if (!rst_n) rdy_reg <= 1'b1; + else begin + if (rdy && ena) rdy_reg <= 1'b0; + if (!rdy && !busy_now) rdy_reg <= 1'b1; + end + + endmodule -- cgit v1.2.3