From 657678ac85785aedeb53001ec4e5d2813cd5270a Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Wed, 23 Oct 2019 16:59:30 +0300 Subject: Added simulation-only code to measure multiplier load. --- rtl/modexpng_core_top.v | 4 +++- rtl/modexpng_mmm_dual.v | 12 ++++++++++++ rtl/modexpng_uop_engine.v | 6 ++---- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/rtl/modexpng_core_top.v b/rtl/modexpng_core_top.v index 18c32bb..7fdb3c5 100644 --- a/rtl/modexpng_core_top.v +++ b/rtl/modexpng_core_top.v @@ -112,7 +112,7 @@ module modexpng_core_top // uOP Engine // `ifdef MODEXPNG_ENABLE_DEBUG - wire [1:0] uop_decoded_stop; + wire uop_decoded_stop; `endif modexpng_uop_engine uop_engine @@ -125,6 +125,8 @@ module modexpng_core_top `ifdef MODEXPNG_ENABLE_DEBUG .uop_decoded_stop (uop_decoded_stop), + `else + .uop_decoded_stop (), `endif .crt_mode (crt_mode), diff --git a/rtl/modexpng_mmm_dual.v b/rtl/modexpng_mmm_dual.v index a868362..9b6695a 100644 --- a/rtl/modexpng_mmm_dual.v +++ b/rtl/modexpng_mmm_dual.v @@ -994,5 +994,17 @@ module modexpng_mmm_dual if (rdy && ena) rdy_reg <= 1'b0; if (!rdy && (fsm_state == MMM_FSM_STATE_STOP)) rdy_reg <= 1'b1; end + + + // + // Debug + // + `ifdef MODEXPNG_ENABLE_DEBUG + real load_cyc_mult = 0.0; + always @(posedge clk) + // + if (dsp_xy_ce_m) + load_cyc_mult <= load_cyc_mult + 1.0; + `endif endmodule diff --git a/rtl/modexpng_uop_engine.v b/rtl/modexpng_uop_engine.v index c7b064a..ae88d1a 100644 --- a/rtl/modexpng_uop_engine.v +++ b/rtl/modexpng_uop_engine.v @@ -6,9 +6,7 @@ module modexpng_uop_engine ena, rdy, - `ifdef MODEXPNG_ENABLE_DEBUG uop_decoded_stop, - `endif crt_mode, @@ -88,9 +86,7 @@ module modexpng_uop_engine input ena; output rdy; - `ifdef MODEXPNG_ENABLE_DEBUG output uop_decoded_stop; - `endif input crt_mode; @@ -312,6 +308,8 @@ module modexpng_uop_engine // `ifdef MODEXPNG_ENABLE_DEBUG assign uop_decoded_stop = (uop_fsm_state == UOP_FSM_STATE_DECODE) && uop_opcode_is_stop; + `else + assign uop_decoded_stop = 1'b0; `endif -- cgit v1.2.3