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path: root/rtl/modexpng_reductor.v
AgeCommit message (Collapse)Author
2020-01-30Accomodate the changes to DSP slice wrappers.Pavel V. Shatov (Meister)
2020-01-21Refactored modular reductor module.Pavel V. Shatov (Meister)
2019-11-20Small change to the reductor module to try to get past 180 MHz. Previously BRAMPavel V. Shatov (Meister)
outputs were going directry into a LUT-based ternary adder which was causing timing problems. Added a layer of flip-flops, so instead of BRAM -> LUT -> FF we have BRAM -> FF -> LUT -> FF. This increases core latency by (number_of_supporting_modular_multiplications + number_of_exponent_bits) ticks.
2019-11-18Refactored reductor module.Pavel V. Shatov (Meister)
2019-10-23Added missing copyright headers.Pavel V. Shatov (Meister)
2019-10-21Further work:Pavel V. Shatov (Meister)
- added core wrapper - fixed module resets across entire core (all the resets are now consistently active-low) - continued refactoring
2019-10-21Entire CRT signature algorithm works by now.Pavel V. Shatov (Meister)
Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled.
2019-10-03Added more micro-operations, also added "general worker" module. The worker ↵Pavel V. Shatov (Meister)
is basically a block memory data mover, but it can also do some supporting operations required for the Garner's formula part of the exponentiation.
2019-10-03Reworked storage architecture (moved I/O memory to a separate module, since ↵Pavel V. Shatov (Meister)
there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication.
2019-10-01Redesigned core architecture, unified bank structure. All storage blocks nowPavel V. Shatov (Meister)
have eight 4kbit entries and occupy one 36K BRAM tile.
2019-10-01Major rewrite (different core hierarchy, buses, wrappers, etc).Pavel V. Shatov (Meister)