user/shatov/modexpng - "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA

Age	Commit message (Collapse)	Author
2020-01-21	Added more meaningful constants to avoid certain hardcoded numbers.	Pavel V. Shatov (Meister)

2019-10-23	Added missing copyright headers.	Pavel V. Shatov (Meister)

2019-10-21	Further work:	Pavel V. Shatov (Meister)
	- added core wrapper - fixed module resets across entire core (all the resets are now consistently active-low) - continued refactoring
2019-10-21	Entire CRT signature algorithm works by now.	Pavel V. Shatov (Meister)
	Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled.
2019-10-03	Added more micro-operations, entire Montgomery exponentiation ladder works now.	Pavel V. Shatov (Meister)

2019-10-03	Added more micro-operations, also added "general worker" module. The worker ↵	Pavel V. Shatov (Meister)
	is basically a block memory data mover, but it can also do some supporting operations required for the Garner's formula part of the exponentiation.
2019-10-03	Expanded micro-operation parameters (added dedicated control bit to force ↵	Pavel V. Shatov (Meister)
	the B input of the modular multiplier to 1, this is necessary to bring numbers out of Montgomery domain).
2019-10-03	Reworked storage architecture (moved I/O memory to a separate module, since ↵	Pavel V. Shatov (Meister)
	there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication.
2019-10-03	Redesigned storage modules, added top-level module, added I/O storage space.	Pavel V. Shatov (Meister)

2019-10-01	Redesigned core architecture, unified bank structure. All storage blocks now	Pavel V. Shatov (Meister)
	have eight 4kbit entries and occupy one 36K BRAM tile.
2019-10-01	Major rewrite (different core hierarchy, buses, wrappers, etc).	Pavel V. Shatov (Meister)

2019-10-01	Implemented the final stage of the Montgomery modular multiplication, i.e.	Pavel V. Shatov (Meister)
	addition of AB and M then reduction by right-shift.
2019-10-01	Further work on the Montgomery modular multiplier. Added the third	Pavel V. Shatov (Meister)
	"rectangular" stage of the multiplication process, i.e. computation of how many copies of the modulus N to add to the intermediate product AB to zeroize the lower half: M = Q * N.
2019-10-01	Started working on the pipelined Montgomery modular multiplier. Currently can	Pavel V. Shatov (Meister)
	do the "square" part of the multiplication, i.e. compute the twice larger intermediate product AB = A * B.