user/shatov/modexpng - "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA

Age	Commit message (Collapse)	Author
2019-10-03	Reworked storage architecture (moved I/O memory to a separate module, since ↵	Pavel V. Shatov (Meister)
	there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication.
2019-10-03	Redesigned storage modules, added top-level module, added I/O storage space.	Pavel V. Shatov (Meister)

2019-10-01	Redesigned core architecture, unified bank structure. All storage blocks now	Pavel V. Shatov (Meister)
	have eight 4kbit entries and occupy one 36K BRAM tile.
2019-10-01	Major rewrite (different core hierarchy, buses, wrappers, etc).	Pavel V. Shatov (Meister)

2019-10-01	Implemented the final stage of the Montgomery modular multiplication, i.e.	Pavel V. Shatov (Meister)
	addition of AB and M then reduction by right-shift.
2019-10-01	Further work on the Montgomery modular multiplier. Added the third	Pavel V. Shatov (Meister)
	"rectangular" stage of the multiplication process, i.e. computation of how many copies of the modulus N to add to the intermediate product AB to zeroize the lower half: M = Q * N.
2019-10-01	Started working on the pipelined Montgomery modular multiplier. Currently can	Pavel V. Shatov (Meister)
	do the "square" part of the multiplication, i.e. compute the twice larger intermediate product AB = A * B.