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2019-10-21Reworked testbench, clk_sys and clk_core can now have any ratio, notPavel V. Shatov (Meister)
necessarily 1:2. Fixed compile-time issue where ISE fails to place two DSP slices next to each other, if A and/or B cascade path(s) between then are partially connected. Basically, if cascade is used, entire bus must be connected.
2019-10-21Redesigned the testbench. Core clock does not necessarily need to be twicePavel V. Shatov (Meister)
faster than the bus clock now. It can be the same, or say four times faster.