| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-10-21 | Reworked testbench, clk_sys and clk_core can now have any ratio, not | Pavel V. Shatov (Meister) | |
| necessarily 1:2. Fixed compile-time issue where ISE fails to place two DSP slices next to each other, if A and/or B cascade path(s) between then are partially connected. Basically, if cascade is used, entire bus must be connected. | |||
| 2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) | |
| faster than the bus clock now. It can be the same, or say four times faster. | |||
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index : user/shatov/modexpng | |
| "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA | git repositories |
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