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-rw-r--r--rtl/modexpng_dsp_array_block.v12
-rw-r--r--rtl/modexpng_dsp_slice_wrapper_xilinx.v18
-rw-r--r--rtl/modexpng_uop_rom.v2
-rw-r--r--rtl/modexpng_wrapper.v246
4 files changed, 172 insertions, 106 deletions
diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v
index 1444aa7..2724a68 100644
--- a/rtl/modexpng_dsp_array_block.v
+++ b/rtl/modexpng_dsp_array_block.v
@@ -24,8 +24,8 @@ module modexpng_dsp_array_block
input [ WORD_W -1:0] b;
output [NUM_MULTS_AUX * MAC_W -1:0] p;
- wire [WORD_EXT_W -1:0] casc_a[0:NUM_MULTS_HALF-1];
- wire [ WORD_W -1:0] casc_b[0:NUM_MULTS_HALF-1];
+ wire [DSP48E1_A_W -1:0] casc_a[0:NUM_MULTS_HALF-1];
+ wire [DSP48E1_B_W -1:0] casc_b[0:NUM_MULTS_HALF-1];
wire ce_a0 = ce_a;
reg ce_a1 = 1'b0;
@@ -70,8 +70,8 @@ module modexpng_dsp_array_block
.opmode ({1'b0, mode_z[2*z], 1'b0, 2'b01, 2'b01}),
.alumode ({DSP48E1_ALUMODE_W{1'b0}}),
- .casc_a_in (WORD_EXT_ZERO),
- .casc_b_in (WORD_ZERO),
+ .casc_a_in (),
+ .casc_b_in (),
.casc_a_out (casc_a[z]),
.casc_b_out (casc_b[z])
@@ -138,8 +138,8 @@ module modexpng_dsp_array_block
.opmode ({1'b0, mode_z[2*NUM_MULTS_HALF], 1'b0, 2'b01, 2'b01}),
.alumode ({DSP48E1_ALUMODE_W{1'b0}}),
- .casc_a_in (WORD_EXT_ZERO),
- .casc_b_in (WORD_ZERO),
+ .casc_a_in (),
+ .casc_b_in (),
.casc_a_out (),
.casc_b_out ()
diff --git a/rtl/modexpng_dsp_slice_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_wrapper_xilinx.v
index 9c1a60d..8c0b969 100644
--- a/rtl/modexpng_dsp_slice_wrapper_xilinx.v
+++ b/rtl/modexpng_dsp_slice_wrapper_xilinx.v
@@ -30,13 +30,11 @@ module modexpng_dsp_slice_wrapper_xilinx #
input [ DSP48E1_INMODE_W -1:0] inmode;
input [ DSP48E1_OPMODE_W -1:0] opmode;
input [DSP48E1_ALUMODE_W -1:0] alumode;
- input [ WORD_EXT_W -1:0] casc_a_in;
- input [ WORD_W -1:0] casc_b_in;
- output [ WORD_EXT_W -1:0] casc_a_out;
- output [ WORD_W -1:0] casc_b_out;
+ input [ DSP48E1_A_W -1:0] casc_a_in;
+ input [ DSP48E1_B_W -1:0] casc_b_in;
+ output [ DSP48E1_A_W -1:0] casc_a_out;
+ output [ DSP48E1_B_W -1:0] casc_b_out;
- wire [DSP48E1_A_W - WORD_EXT_W -1:0] casc_a_dummy;
- wire [DSP48E1_B_W - WORD_W -1:0] casc_b_dummy;
wire [DSP48E1_P_W - MAC_W -1:0] p_dummy;
DSP48E1 #
@@ -99,10 +97,10 @@ module modexpng_dsp_slice_wrapper_xilinx #
.OPMODE (opmode),
.ALUMODE (alumode),
- .ACIN ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, casc_a_in}),
- .BCIN ({{(DSP48E1_B_W-WORD_W){1'b0}}, casc_b_in}),
- .ACOUT ({casc_a_dummy, casc_a_out}),
- .BCOUT ({casc_b_dummy, casc_b_out}),
+ .ACIN (casc_a_in),
+ .BCIN (casc_b_in),
+ .ACOUT (casc_a_out),
+ .BCOUT (casc_b_out),
.PCIN ({DSP48E1_P_W{1'b0}}),
.PCOUT (),
.CARRYCASCIN (1'b0),
diff --git a/rtl/modexpng_uop_rom.v b/rtl/modexpng_uop_rom.v
index c15f608..74f7ea3 100644
--- a/rtl/modexpng_uop_rom.v
+++ b/rtl/modexpng_uop_rom.v
@@ -134,7 +134,7 @@ module modexpng_uop_rom
7'd080: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_XM }; //
7'd081: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_YM }; //
- //
+
7'd082: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_11, BANK_WIDE_E, BANK_NARROW_B, BANK_WIDE_C, BANK_NARROW_C }; //
7'd083: data <= {UOP_OPCODE_INPUT_TO_WIDE, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_IN_1_N_FACTOR, BANK_WIDE_A, BANK_DNC }; //
diff --git a/rtl/modexpng_wrapper.v b/rtl/modexpng_wrapper.v
index 687a963..0af6c32 100644
--- a/rtl/modexpng_wrapper.v
+++ b/rtl/modexpng_wrapper.v
@@ -111,7 +111,8 @@ module modexpng_wrapper
//
localparam MIN_OP_W = 2 * NUM_MULTS * WORD_W * 2;
localparam MIN_EXP_W = 2 * 2;
- localparam ZEROES_BIT_INDEX_W = 1 + cryptech_clog2(NUM_MULTS) + cryptech_clog2(WORD_W);
+ localparam LSB_BIT_INDEX_W = 1 + cryptech_clog2(NUM_MULTS) + cryptech_clog2(WORD_W);
+ localparam MSB_BIT_INDEX_W = BIT_INDEX_W - LSB_BIT_INDEX_W;
//
@@ -125,35 +126,29 @@ module modexpng_wrapper
//
// Registers
//
- reg wrap_reg_control = `MODEXPNG_DEFAULT_CONTROL;
- reg sync_reg_control = `MODEXPNG_DEFAULT_CONTROL;
- reg sync_reg_control_dly = `MODEXPNG_DEFAULT_CONTROL;
- reg core_reg_control = `MODEXPNG_DEFAULT_CONTROL;
- reg wrap_reg_mode = `MODEXPNG_DEFAULT_MODE;
+ reg wrap_reg_control = `MODEXPNG_DEFAULT_CONTROL;
+ reg core_reg_control = `MODEXPNG_DEFAULT_CONTROL;
+ reg wrap_reg_mode = `MODEXPNG_DEFAULT_MODE;
reg sync_reg_mode;
reg core_reg_mode;
- reg [BIT_INDEX_W:ZEROES_BIT_INDEX_W] wrap_modulus_bits_msb;
- reg [BIT_INDEX_W: 0] wrap_exponent_bits;
+ reg [BIT_INDEX_W:LSB_BIT_INDEX_W] wrap_modulus_bits_msb;
+ reg [BIT_INDEX_W: 0] wrap_exponent_bits;
- initial write_modulus_bits(`MODEXPNG_DEFAULT_MODULUS_BITS);
- initial write_exponent_bits(`MODEXPNG_DEFAULT_EXPONENT_BITS);
-
- wire sync_reg_control_rising = sync_reg_control & ~sync_reg_control_dly;
+ initial update_modulus_bits_user;
+ initial update_exponent_bits_user;
+
+ //wire sync_reg_control_rising = sync_reg_control & ~sync_reg_control_dly;
//
// Wires
//
- reg wrap_reg_status = 1'b1;
- reg sync_reg_status = 1'b1;
+ reg wrap_reg_status = 1'b1;
+ reg sync_reg_status = 1'b1;
+ reg sync_reg_status_dly = 1'b1;
wire core_reg_status;
- always @(posedge clk or negedge rst_n)
- //
- if (!rst_n) {wrap_reg_status, sync_reg_status} <= { 1'b1, 1'b1};
- else {wrap_reg_status, sync_reg_status} <= {sync_reg_status, core_reg_status};
-
//
// Output Mux
@@ -175,8 +170,76 @@ module modexpng_wrapper
else core_rst_shreg <= {core_rst_shreg[14:0], 1'b1};
assign core_rst_n = core_rst_shreg[15];
+
+
+ //
+ // Trigger Logic
+ //
+ reg wrap_reg_control_dly = `MODEXPNG_DEFAULT_CONTROL;
+ reg wrap_reg_control_posedge = 1'b0;
+ reg sync_reg_control_posedge = 1'b0;
+ reg core_reg_control_posedge = 1'b0;
+ reg core_reg_control_posedge_dly = 1'b0;
+ reg sync_reg_control_posedge_ack = 1'b0;
+ reg wrap_reg_control_posedge_ack = 1'b0;
+
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) wrap_reg_control_dly <= `MODEXPNG_DEFAULT_CONTROL;
+ else wrap_reg_control_dly <= wrap_reg_control;
+
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) wrap_reg_control_posedge <= 1'b0;
+ else begin
+ if (!wrap_reg_control_posedge) begin
+ if (wrap_reg_control && !wrap_reg_control_dly) wrap_reg_control_posedge <= 1'b1;
+ end else begin
+ if (wrap_reg_control_posedge_ack) wrap_reg_control_posedge <= 1'b0;
+ end
+ end
+
+ always @(posedge clk_core or negedge core_rst_n)
+ if (!core_rst_n) sync_reg_control_posedge <= 1'b0;
+ else sync_reg_control_posedge <= wrap_reg_control_posedge;
+
+ always @(posedge clk_core or negedge core_rst_n)
+ if (!core_rst_n) core_reg_control_posedge <= 1'b0;
+ else core_reg_control_posedge <= sync_reg_control_posedge;
+
+ always @(posedge clk_core or negedge core_rst_n)
+ if (!core_rst_n) core_reg_control_posedge_dly <= 1'b0;
+ else core_reg_control_posedge_dly <= core_reg_control_posedge;
+
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) sync_reg_control_posedge_ack <= 1'b0;
+ else sync_reg_control_posedge_ack <= core_reg_control_posedge;
+
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) wrap_reg_control_posedge_ack <= 1'b0;
+ else wrap_reg_control_posedge_ack <= sync_reg_control_posedge_ack;
+
+ always @(posedge clk_core or negedge core_rst_n)
+ if (!core_rst_n) core_reg_control <= `MODEXPNG_DEFAULT_CONTROL;
+ else core_reg_control <= core_reg_control_posedge && !core_reg_control_posedge_dly;
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) sync_reg_status <= 1'b1;
+ else sync_reg_status <= core_reg_status;
+
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) sync_reg_status_dly <= 1'b1;
+ else sync_reg_status_dly <= sync_reg_status;
+
+ always @(posedge clk or negedge rst_n)
+ if (!rst_n) wrap_reg_status <= 1'b1;
+ else begin
+ if (wrap_reg_status) begin
+ if (wrap_reg_control && !wrap_reg_control_dly) wrap_reg_status <= 1'b0;
+ end else begin
+ if (!wrap_reg_control_posedge && !wrap_reg_control_posedge_ack && sync_reg_status_dly) wrap_reg_status <= 1'b1;
+ end
+ end
+
//
// Parameters Resync
//
@@ -212,7 +275,7 @@ module modexpng_wrapper
always @(posedge clk_core)
//
- if (sync_reg_control_rising) begin
+ if (core_reg_control_posedge && !core_reg_control_posedge_dly) begin
//
core_reg_mode <= sync_reg_mode;
//
@@ -224,21 +287,6 @@ module modexpng_wrapper
//
end
-
- //
- // Trigger Logic
- //
- always @(posedge clk_core or negedge rst_n)
- //
- if (!rst_n) {sync_reg_control_dly, sync_reg_control} <= {`MODEXPNG_DEFAULT_CONTROL, `MODEXPNG_DEFAULT_CONTROL};
- else {sync_reg_control_dly, sync_reg_control} <= { sync_reg_control, wrap_reg_control};
-
- always @(posedge clk_core or negedge rst_n)
- //
- if (!rst_n) core_reg_control <= `MODEXPNG_DEFAULT_CONTROL;
- else core_reg_control <= sync_reg_control_rising;
-
-
//
// ModExpNG
//
@@ -271,6 +319,63 @@ module modexpng_wrapper
//
// Write Interface
//
+
+ wire [ BIT_INDEX_W :0] corrected_modulus_bits_user = correct_modulus_bits(write_data[BIT_INDEX_W:0]);
+ wire [MSB_BIT_INDEX_W :0] corrected_modulus_bits_msb_user = corrected_modulus_bits_user[BIT_INDEX_W:LSB_BIT_INDEX_W];
+ wire [ OP_ADDR_W :0] modulus_num_words_n_user = {corrected_modulus_bits_msb_user, {(LSB_BIT_INDEX_W-WORD_MUX_W){1'b0}}} - 1'b1;
+ wire [ OP_ADDR_W-1:0] modulus_num_words_n_lsb_user = modulus_num_words_n_user[OP_ADDR_W-1:0];
+ wire [ OP_ADDR_W-1:0] modulus_num_words_pq_user = {corrected_modulus_bits_msb_user, {(LSB_BIT_INDEX_W-WORD_MUX_W-1){1'b0}}} - 1'b1;
+
+ wire [ BIT_INDEX_W :0] corrected_modulus_bits_default = `MODEXPNG_DEFAULT_MODULUS_BITS;
+ wire [MSB_BIT_INDEX_W :0] corrected_modulus_bits_msb_default = corrected_modulus_bits_default[BIT_INDEX_W:LSB_BIT_INDEX_W];
+ wire [ OP_ADDR_W :0] modulus_num_words_n_default = {corrected_modulus_bits_msb_default, {(LSB_BIT_INDEX_W-WORD_MUX_W){1'b0}}} - 1'b1;
+ wire [ OP_ADDR_W-1:0] modulus_num_words_n_lsb_default = modulus_num_words_n_default[OP_ADDR_W-1:0];
+ wire [ OP_ADDR_W-1:0] modulus_num_words_pq_default = {corrected_modulus_bits_msb_default, {(LSB_BIT_INDEX_W-WORD_MUX_W-1){1'b0}}} - 1'b1;
+
+ wire [ BIT_INDEX_W :0] corrected_exponent_bits_user = correct_exponent_bits(write_data[BIT_INDEX_W:0]);
+ wire [ BIT_INDEX_W-1:0] corrected_exponent_bits_msb_user = corrected_exponent_bits_user[BIT_INDEX_W:1];
+ wire [ BIT_INDEX_W :0] exponent_num_bits_n_user = corrected_exponent_bits_user - 1'b1;
+ wire [ BIT_INDEX_W-1:0] exponent_num_bits_n_lsb_user = exponent_num_bits_n_user[BIT_INDEX_W-1:0];
+ wire [ BIT_INDEX_W-1:0] exponent_num_bits_pq_user = corrected_exponent_bits_msb_user - 1'b1;
+
+ wire [ BIT_INDEX_W :0] corrected_exponent_bits_default = `MODEXPNG_DEFAULT_EXPONENT_BITS;
+ wire [ BIT_INDEX_W-1:0] corrected_exponent_bits_msb_default = corrected_exponent_bits_default[BIT_INDEX_W:1];
+ wire [ BIT_INDEX_W :0] exponent_num_bits_n_default = corrected_exponent_bits_default - 1'b1;
+ wire [ BIT_INDEX_W-1:0] exponent_num_bits_n_lsb_default = exponent_num_bits_n_default[BIT_INDEX_W-1:0];
+ wire [ BIT_INDEX_W-1:0] exponent_num_bits_pq_default = corrected_exponent_bits_msb_default - 1'b1;
+
+ task update_modulus_bits_user;
+ begin
+ wrap_modulus_bits_msb <= corrected_modulus_bits_msb_user;
+ wrap_word_index_last_n <= modulus_num_words_n_lsb_user;
+ wrap_word_index_last_pq <= modulus_num_words_pq_user;
+ end
+ endtask
+
+ task update_modulus_bits_default;
+ begin
+ wrap_modulus_bits_msb <= corrected_modulus_bits_msb_default;
+ wrap_word_index_last_n <= modulus_num_words_n_lsb_default;
+ wrap_word_index_last_pq <= modulus_num_words_pq_default;
+ end
+ endtask
+
+ task update_exponent_bits_user;
+ begin
+ wrap_exponent_bits <= corrected_exponent_bits_user;
+ wrap_bit_index_last_n <= exponent_num_bits_n_lsb_user;
+ wrap_bit_index_last_pq <= exponent_num_bits_pq_user;
+ end
+ endtask
+
+ task update_exponent_bits_default;
+ begin
+ wrap_exponent_bits <= corrected_exponent_bits_default;
+ wrap_bit_index_last_n <= exponent_num_bits_n_lsb_default;
+ wrap_bit_index_last_pq <= exponent_num_bits_pq_default;
+ end
+ endtask
+
always @(posedge clk or negedge rst_n)
//
if (!rst_n) begin
@@ -278,77 +383,40 @@ module modexpng_wrapper
wrap_reg_control <= `MODEXPNG_DEFAULT_CONTROL;
wrap_reg_mode <= `MODEXPNG_DEFAULT_MODE;
//
- write_modulus_bits(`MODEXPNG_DEFAULT_MODULUS_BITS);
- write_exponent_bits(`MODEXPNG_DEFAULT_EXPONENT_BITS);
+ update_modulus_bits_default;
+ update_exponent_bits_default;
//
end else if (cs && we && addr_msb_is_wrap)
//
case (addr_lsb)
ADDR_CONTROL: wrap_reg_control <= write_data[CONTROL_NEXT_BIT];
ADDR_MODE: wrap_reg_mode <= write_data[MODE_FULLCRT_BIT];
- ADDR_MODULUS_BITS: write_modulus_bits(write_data[BIT_INDEX_W:0]);
- ADDR_EXPONENT_BITS: write_exponent_bits(write_data[BIT_INDEX_W:0]);
+ ADDR_MODULUS_BITS: update_modulus_bits_user;
+ ADDR_EXPONENT_BITS: update_exponent_bits_user;
endcase
//
- // Update modulus width
+ // Only accept correct modulus width
//
- function [BIT_INDEX_W:ZEROES_BIT_INDEX_W] fix_modulus_bits;
- input [BIT_INDEX_W: 0] width;
- if (width < MIN_OP_W) fix_modulus_bits = MIN_OP_W[BIT_INDEX_W:ZEROES_BIT_INDEX_W];
- else if (width > MAX_OP_W) fix_modulus_bits = MAX_OP_W[BIT_INDEX_W:ZEROES_BIT_INDEX_W];
- else fix_modulus_bits = width [BIT_INDEX_W:ZEROES_BIT_INDEX_W];
- endfunction
-
- function [OP_ADDR_W-1: 0] calc_modulus_num_words_n;
- input [BIT_INDEX_W:ZEROES_BIT_INDEX_W] width;
- calc_modulus_num_words_n = {width, {(ZEROES_BIT_INDEX_W-WORD_MUX_W){1'b0}}} - 1'b1; // truncates msb
- endfunction
-
- function [OP_ADDR_W-1: 0] calc_modulus_num_words_pq;
- input [BIT_INDEX_W:ZEROES_BIT_INDEX_W] width;
- calc_modulus_num_words_pq = {width, {(ZEROES_BIT_INDEX_W-WORD_MUX_W-1){1'b0}}} - 1'b1; // fits exactly
- endfunction
-
- task write_modulus_bits;
+ function [BIT_INDEX_W:0] correct_modulus_bits;
input [BIT_INDEX_W:0] width;
- begin
- wrap_modulus_bits_msb <= fix_modulus_bits(width);
- wrap_word_index_last_n <= calc_modulus_num_words_n(fix_modulus_bits(width));
- wrap_word_index_last_pq <= calc_modulus_num_words_pq(fix_modulus_bits(width));
- end
- endtask
+ if (width < MIN_OP_W) correct_modulus_bits = MIN_OP_W;
+ else if (width > MAX_OP_W) correct_modulus_bits = MAX_OP_W;
+ else correct_modulus_bits = width;
+ endfunction
//
- // Update exponent width
+ // Only accept correct exponent width
//
- function [BIT_INDEX_W:0] fix_exponent_bits;
+ function [BIT_INDEX_W:0] correct_exponent_bits;
input [BIT_INDEX_W:0] width;
- if (width < MIN_EXP_W) fix_exponent_bits = MIN_EXP_W;
- else if (width > MAX_OP_W ) fix_exponent_bits = MAX_OP_W;
- else fix_exponent_bits = width;
- endfunction
-
- function [BIT_INDEX_W-1:0] calc_exponent_num_bits_n;
- input [BIT_INDEX_W :0] width;
- calc_exponent_num_bits_n = width - 1'b1; // truncates msb
- endfunction
-
- function [BIT_INDEX_W-1:0] calc_exponent_num_bits_pq;
- input [BIT_INDEX_W: 0] width;
- calc_exponent_num_bits_pq = width[BIT_INDEX_W:1] - 1'b1; // fits exactly
+ if (width < MIN_EXP_W) correct_exponent_bits = MIN_EXP_W;
+ else if (width > MAX_OP_W ) correct_exponent_bits = MAX_OP_W;
+ else correct_exponent_bits = width;
endfunction
-
- task write_exponent_bits;
- input [BIT_INDEX_W:0] width;
- begin
- wrap_exponent_bits <= fix_exponent_bits(width);
- wrap_bit_index_last_n <= calc_exponent_num_bits_n(fix_exponent_bits(width));
- wrap_bit_index_last_pq <= calc_exponent_num_bits_pq(fix_exponent_bits(width));
- end
- endtask
+
//
@@ -367,7 +435,7 @@ module modexpng_wrapper
ADDR_STATUS: wrap_read_data <= {{30{1'b0}}, wrap_reg_status, 1'b1};
//
ADDR_MODE: wrap_read_data <= {{30{1'b0}}, wrap_reg_mode, 1'b0};
- ADDR_MODULUS_BITS: wrap_read_data <= {{(31-BIT_INDEX_W){1'b0}}, wrap_modulus_bits_msb, {ZEROES_BIT_INDEX_W{1'b0}}};
+ ADDR_MODULUS_BITS: wrap_read_data <= {{(31-BIT_INDEX_W){1'b0}}, wrap_modulus_bits_msb, {LSB_BIT_INDEX_W{1'b0}}};
ADDR_EXPONENT_BITS: wrap_read_data <= {{(31-BIT_INDEX_W){1'b0}}, wrap_exponent_bits};
ADDR_BANK_BITS: wrap_read_data <= MAX_OP_W;
ADDR_NUM_MULTS: wrap_read_data <= NUM_MULTS;